Resources

Slides

These slides are from older offerings of the course, but might still be useful to you. You are still responsible for material discussed in class and assigned in readings.

Slides

Project resources

1 Documentation for the Xilinx ISE Tools

  1. ISE In-Depth Tutorial - This is somewhat out of date, but still has lots of good info.

  2. Spartan-3E Libraries Guide for Schematic Designs
  3. ISim User Guide
  4. Command Line Tools User Guide
  5. XST User Guide
  6. Synthesis and Simulation Design Guide

2 Documentation for the Spartan 3E Starter Board

  1. Spartan-3E Starter Kit Board User Guide
  2. Spartan-3E Starter Schematic

3 Example Basic Building Blocks

  1. Mux (schematic, project) - A multiplexor which selects between 8, 16-bit busses.

  2. Register (schematic, project) - A 16-bit register.

  3. Register file ( schematic, project) - A register file containing 8, 16-bit registers. Register 0 is hardwired to zero. Two registers can be read and a third written simultaneously.

    Caution: the constants in the symbol library are 32-bit constants by default and must be edited for different widths using a text editor. Change the BitVector trait to the desired width.

  4. Constant ( schematic, project) - A 16-bit constant with the value of 0x0001.

    Note: the value is built using gnd and vcc to get a 0 and 1 respectively. A 16-bit buffer (schematic) is needed as a ``name changer'' so that the output pin can have a reasonable name.

  5. Memory -
    1. Distributed memory ( project ) - Distributed memory built with the core generator and initialized with memory.coe. Distributed memory is fast (an address can be presented after the rising edge of the clock and the data at that address available before the next rising edge), but expensive (it consumes a lot of fpga resources).

    2. Block memory ( project ) - Block memory built with the core generator and initialized with memory.coe. Block memory is synchronous (i.e. once an address is presented the data at that address is not available until after the next rising edge of the clock - this looks like a one cycle delay), but is cheap (it is a dedicated resource on chip and consumes no fpga resources).

    Caution: Both the distributed and block memory use a memory initialization file. Xilinx frequently stores an absolute path to this file. If you get an error trying to open the core generated memory indicating that Xilinx can't find something like ``/home/mellor/ProfessionalArchives/Teaching/Class/.../memory_small.coe''. Then use notepad to edit the path in the .xco file (it's in the ipcore_dir) to something like ``../memory_small.coe,'' save it, and try opening it again.

    Note: It is feasible to run block memory at twice the clock rate as your processor which will work around the synchronous issue.

  6. Interrupt register ( schematic, project ) - A 16-bit register which supports 4 levels of interrupt.

    15     10 9 8 7 6 5 4 3 2 1 0
    unused IL IE IM3 IM2 IM1 IM0 I3 I2 I1 I0

    IL is the interrupt level and is a zero when the system is handling an interrupt and a one otherwise. When the interrupt level is a zero interrupts are blocked. IE is the interrupt enable. Setting the interrupt enable to one turns on interrupts and a zero turns them off. IM? is the interrupt mask. Setting the interrupt mask for a particular level to zero will block interrupts at that level. I? is the interrupt request. A one indicates that an interrupt is pending.

    The project includes a test schematic which works on the fpga board.

4 Miscellaneous Schematic Designs

  1. ALU and LCD display ( schematic, project ) - this design implements a 16-bit alu and displays the inputs, the operation and the results on the lcd display. The north button resets the lcd display, the south button clears the display, the west button writes the display, the rotary switch increments or decrements the current digit of the display, pushing the rotary switch changes the current digit, switch 0 selects the direction when the rotary button is pushed, switch 1 selects which row is displayed, led 7 indicates that the lcd driver is ready, led 6 is the zero detector, and led 5 is overflow.

  2. Barebones LCD display ( schematic, project ) - this design demonstrates the lcd display, switches and leds.

  3. Rotary counter and LCD display ( schematic, project ) - this design counts up and down when the rotary switch is turned. Push the rotary switch to change digits. The value is displayed on the LCD.

  4. Switch debouncer ( schematic, project ) - this design demonstrates a debouncer suitable for the switches (push button and slide) on the Spartan boards.

  5. Rotary switch debouncer ( schematic, project ) - this design demonstrates a debouncer suitable for the rotary switch on the Spartan boards.

    Warning: All of these designs use core generated parts from an older core generator. For core generated parts (.xco), you should include all of the files of the same name with various extensions (e.g. .asy, .mif, .ngc, .v).

5 Example Verilog Designs

  1. State machine (verilog) - this design contains a partial implementation of a MIPS multicycle control unit.

  2. Memory (verilog, memory initialization, memory contents) - this design contains a simple memory implementation similar to that produced by the distributed memory generator in the core generator generator.

    Caution: this means of implementing memory consumes a large amount of resources.

6 Tips

  1. The following verilog code may be helpful in creating test benches. 

       // use this if your design contains sequential logic
   parameter   PERIOD = 20;
   parameter   real DUTY_CYCLE = 0.5;
   parameter   OFFSET = 10;
   
   initial    // Clock process for CLK
     begin
        #OFFSET;
        forever
          begin
             CLK = 1'b0;
             #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;
             #(PERIOD*DUTY_CYCLE);
          end
     end
   
   initial begin
      // Initialize Inputs

      // Wait 100ns for simulator to finish initializing 
      #100;

      // Enter test values
   end

    Caution: The simulator takes 100ns of simulation time to initialize. Other than setting initial values, you should not do any tests in the first 100ns.

  2. The user constraint file (.ucf) contains the mapping between physical pins and input/output net names. ``aluIO.ucf'' in the aluIO project is a good example.

  3. When two wires or busses (nets) are connected, they are given a common name. If you later decide to separate the net, you need to delete at least one of the nets completely and replace it. If you don’t do this, Xilinx will continue to consider them connected because they share a common net name.

    You can use ``Find'' to highlight the entire net.

  4. Extraneous source files in the project can cause problems.

  5. Occasionally it may look as if wires in the schematic disappear. Try refreshing the screen by pressing the F5 key.

  6. Be careful in selecting net names. Capitalization matters. Verilog or VHDL reserved words (e.g. ``input'' ``output'') cannot be used. In addition, it appears that ``FSM'' is also reserved and should not be used. You can combine signals by listing them in the name of a net, e.g. X(15:11),Y(10:0).

  7. Pins must have well formed names and within one schematic or symbol they must be unique. A(15:0) is a valid pin name, but not X(15:11),Y(10:0). If you have a net named X(15:11),Y(10:0) that you want to output to a pin, use a buffer to separate the names.

  8. If your project fails to build for no apparent reason, try Project$\rightarrow$Cleanup Project Files and then rebuild.

  9. It is possible to connect two parts directly together without wire between them, however it may not be possible to add wire later.

  10. If there’s a red box at the end of a wire, the wire is not connected to anything.

  11. When drawing multi-segment wires, clicking a second time on the last point will terminate the wire.

  12. Bus taps can be problematic. Appropriately naming the nets always works.

  13. If you get an error because of a coregen lock file and no coregen process is running, you can simply delete the lock.

  14. The paths to memory initialization files are frequently stored with absolute paths in .xco files. If you are unable to regenerate a core because of the path, simply edit the path.

  15. When generating a memory, a coe file is used as input. The generator then builds the memory and the memory contents are compiled to a mif file. You can edit this file to change the initial memory contents without regenerating the core. However, the mif is a compiled output and may be overwritten during normal project use.

  16. Xilinx won't open project files created with newer versions of Xilinx. Each .xise project file is an XML file and contains the Xilinx version number that created the file. You make projects open in older version of Xilinx by editing the .xise file in a text editor and adjusting the xil_pn:ise_version="14.7" tag near the top of the file.

  17. When you save a schematic or HDL file, the ``undo'' history is cleared.

  18. To select the size of a schematic, right-click on any empty part of the schematic and select ``Object Properties''. Select the desired paper size from the scroll down menu of ``Schematic Properties'' and click ``OK''. It will then give you a warning that this operation cannot be undone and ask if you want to continue. Click ``Yes''.

  19. To erase just part of a wire (not the entire branch), choose ``Select the line segment'' instead of ``select the entire branch'' under ``Select Options''.

  20. If you have difficulty routing a wire, try manually routing it by clicking on ``Use the Manual method...'' under ``Add Wire Options''. You might also try zooming into the area where you want to place it and then try routing it again (either Autoroute or Manual).

  21. If you edit symbols and change the pin layout, make sure that you move the name, the line segment and port (small box) together. You may also want to save a copy of the edited symbol.

  22. To synthesize a module, it must be selected as the ``top module'' in Xilinx Project Navigator. To do so, right-click on the module you’d like to synthesize in the Processes pane in Project navigator and select ``Set as Top Module'' in the pulldown menu. To simulate a subpart of a design, you may need to set the subpart as the top module

  23. Nets that will be connected to physical pins on the fpga (e.g. connections to the lcd, clock and DCM) must be on the top-level schematic.

  24. Incorrect project settings (e.g. family, device, package) can cause a number of synthesis and/or simulation issues.

  25. Paths in Xilinx are limited to 256 characters. If you exceed the path limit, you will need to relocate your project and then manually edit the ``.xise'' file ``Working Directory'' property.