CSSE232 : Computer Architecture I -- Alternate Schedule

1: Mon Dec 01 1

  • Introduction & Course Overview
    • Read Ch 1 (esp. 1.1-1.3, 1.11)
    • Read A.2, A.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
    • Practice A.11; 2.6
  • HW1 review (due Thu Dec 04)
  • Note: HWs are always due at class time.

2: Wed Dec 03 1

  • Intro to RISC-V assembly
  • RISC-V R Types
    • Arithmetic operations
    • Logical operations
    • Read 2.6
    • Practice 2.17-18,20
  • HW2 compiling c into assembly (due Mon Dec 08)
  • RISC-V I-types, immediates, lw and sw
    • Read 2.10 (Important reading)
  • HW3 assembling instructions (due Mon Dec 08)

3: Thu Dec 04 1

4: Mon Dec 08 2

  • RISC-V Branches and Jumps
    • Read 2.7
    • Practice 2.21-22; 2.24; 2.27-28
  • HW4 loops (due Thu Dec 11)
  • Due: * HW2
  • Due: * HW3

5: Wed Dec 10 2

  • Pseudoinstructions
    • Read 2.12 "Assembler" section
  • HW5 pseudoinstructions (due Mon Dec 15)
  • Addressing modes
  • HW6 addressing modes (due Mon Dec 15)

6: Thu Dec 11 2

7: Mon Dec 15 3

  • Procedures
    • Read 2.8; (this is an important reading)
    • Practice 2.29-31; 2.33
  • HW7 procedure calling (due Thu Dec 18)
  • Due: * HW5
  • Due: * HW6

8: Wed Dec 17 3

  • More procedures
    • Read 2.13
  • HW8 procedures and loops (due Mon Jan 05)
  • Practical3 RISC-V Programming (due Thu Jan 08)

9: Thu Dec 18 3

Break

10: Mon Jan 05 4

  • Verilog Survival Guide Videos
    • If you want more, here are old videos (warning, uses Quartus): Video 1 Video 2
  • HW9 write verilog code (due Mon Jan 12)
  • Due: * HW8

11: Wed Jan 07 4

  • Building Single-Cycle datapath (R-types)
    • Read 4.1-3
    • Practice 4.1-4
  • HW10 write relprime (due Wed Jan 14)
  • Practical4 Building and Testing Hardware (due Thu Jan 15)

12: Thu Jan 08 4

13: Mon Jan 12 5

  • More Single-Cycle datapath (I-types and memory)
  • CATME single-cycle team forming survey (due Wed Jan 14)
  • Due: * HW9

14: Wed Jan 14 5

  • Even more Single-Cycle datapath (Branch and Jumps)
  • HW11 adding new single cycle instruction (due Mon Jan 19)
  • Single-Cycle Control
    • Read 4.4
    • Practice 4.4-5
  • HW12 single cycle control (due Wed Jan 21)
  • Due: * HW10
  • Due: * CATME single-cycle team forming survey

15: Thu Jan 15 5

16: Mon Jan 19 6

  • MLK Day (no class)
  • Note: we are skipping HW 13 because of the holiday
  • Due: * HW11

17: Wed Jan 21 6

  • Input/Output
    • Read 2.9
    • Practice 2.38
  • Performance
  • HW14 performance (due Wed Jan 28)
  • Practical6 Single-Cycle Processor II (due Thu Jan 29)
  • CATME single cycle team eval (due Thu Jan 29)
  • Due: * HW12

18: Thu Jan 22 6

19: Mon Jan 26 7

  • Snow day (no class)
  • CATME pipeline team forming survey (due Wed Jan 28)

20: Wed Jan 28 7

  • Pipelined datapath and control
    • Read 4.6-4.7
    • Practice 4.19-20
  • More Pipelined datapath and control
  • Due: * HW14
  • Due: * CATME pipeline team forming survey

21: Thu Jan 29 7

  • Practical7 Pipelined Processor I (due Thu Feb 05)
  • Due: * Practical6
  • Due: * CATME single cycle team eval

22: Mon Feb 02 8

  • Data and control hazards
    • Read 4.8-4.9
    • Practice 4.22; 4.26

23: Wed Feb 04 8

  • More Pipeline Hazards
    • Read 4.8-4.9
  • HW15 pipeline diagrams and efficiency (due Wed Feb 11)
  • Practical8 Pipelined Processor II (due Thu Feb 12)

24: Thu Feb 05 8

25: Mon Feb 09 9

  • Adding Pipelined Instructions
  • HW16 add inst to pipeline (due Mon Feb 16)

26: Wed Feb 11 9

  • Faster Branching with a Pipelined Processor
  • Adding more pipelined instructions
  • Due: * HW15

27: Thu Feb 12 9

28: Mon Feb 16 10

29: Wed Feb 18 10

30: Thu Feb 19 10