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HW11 solution

(20 points) We wish to add a variant of the lw (load word) instruction, which increments the index register after loading the word from memory. This instruction (l_inc) corresponds to the following two instructions:

lw   rd, L(rs1)
addi rs1, rs1, 4

Add any necessary datapaths and control signals to the single-cycle datapath of Figure 4.21, on page 277.

  1. Write the RTL for this new instruction. It may be helpful to review the RTL on the course website.

The RTL for this instruction might look something like:

PC = PC+4
inst = Mem[PC]
a = Reg[ inst[19:15] ]
incremented = a + 4
result = a + SE( inst[31:20] )
memOut = Mem[ result ]
Reg[ inst[11:7] ] = memOut
Reg[ inst[19:15] ] = incremented
  1. Adjust the datapth figure (attached) to execute your RTL. Make modifications as you see reasonably fit. This may include but not limited to adding extra muxes, adders, or ports.

The best solution to this problem is to add a new write capabilities to the register file. The new register file will have a new write address port (5 bits) and a new write data port (32 bits).

This necessitates a new RegWrite signal, so we will have RegWrite1 for the normal data and RegWrite2 for the new ports. This control signal should only be enabled for the new l_inc instruction.

Additionally, a new adder must be added to support the increment by 4 operation. This adder takes as input the output of the register file's first read port and a constant 4. The output is routed to the new write data port on the register file. Finally, the wires for rs1 (inst[19:15]) need to routed to the register file's new write address port.

  1. Provide an updated set of control signals that corresponds to the datapath adjustments you made in the previuos problem. You may add signals to this table as necessary.
Instruction name ALUSrc ALUOp MemtoReg RegWrite MemRead MemWrite RegWrite2
l_inc 1 00 1 1 1 0 1

Modify this figure for your instruction.