CSSE232 : Computer Architecture I
1: Thu Sep 05 1
- Introduction
- Read Ch 1 (esp. 1.1-1.3, 1.11)
- Course Overview
- Read A.2, A.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
- Practice A.11; 2.6
- HW1 review (due Mon Sep 09)
- Note: HWs are always due at class time. There is one shared gradescope for all sections, so the due time on gradescope may not reflect the correct time for all sections.
2: Fri Sep 06 1
- RISC-V green sheet
- Intro to RISC-V assembly
- Read 2.1-2.3
- Practice 2.1-2.4; 2.7-2.8
- Logical operations
- Read 2.6
- Practice 2.17-18,20
- HW2 compiling c into assembly (due Tue Sep 10)
3: Mon Sep 09 1
- Decision instructions
- Read 2.7
- Practice 2.21-22; 2.24; 2.27-28
- HW3 assembling instructions (due Thu Sep 12)
- HW4 assembling more instructions (due Thu Sep 12)
- Due: * HW1
4: Tue Sep 10 1
5: Thu Sep 12 2
- Pseudoinstructions
- Read 2.12 "Assembler" section
- HW5 pseudoinstructions (due Mon Sep 16)
- Due: * HW3
- Due: * HW4
6: Fri Sep 13 2
- Addressing modes
- Read 2.10 (Important reading)
- Practice 2.12; 2.22
- Immediate Translation Handout
- HW6 loops (due Tue Sep 17)
- HW7 addressing modes (due Tue Sep 17)
7: Mon Sep 16 2
8: Tue Sep 17 2
9: Thu Sep 19 3
- Procedures
- Read 2.8; (this is an important reading)
- Practice 2.29-31; 2.33
- HW8 procedure calling (due Mon Sep 23)
10: Fri Sep 20 3
- More procedures
- Read 2.13
- HW9 procedures and loops (due Tue Sep 24)
11: Mon Sep 23 3
12: Tue Sep 24 3
13: Thu Sep 26 4
14: Fri Sep 27 4
- Building a datapath (R-types)
- Read 4.1-3
- Practice 4.1-4
15: Mon Sep 30 4
16: Tue Oct 01 4
- Quiz 2
17: Thu Oct 03 5
- Building a datapath (I-types and memory)
- CATME singlecycle team forming survey (due Fri Oct 04)
18: Fri Oct 04 5
- More Single-Cycle (Branches and Jumps)
- Due: * CATME singlecycle team forming survey
19: Mon Oct 07 5
- Single-Cycle Control
- Read 4.4
- Practice 4.4-5
- Single cycle datapath and control
- Read Single-cycle RTL
- HW12 single cycle control (due Thu Oct 17)
- HW13 add single cycle instruction (due Thu Oct 17)
- Due: * Lab4
20: Tue Oct 08 5
- Lab5 Single-Cycle Processor I (due Thu Oct 17)
21: Mon Oct 14 6
- Other architectures
- Read 2.16-19
- HW10 various architectures (due Thu Oct 17)
22: Tue Oct 15 6
- I/O
- Read 2.9
- Practice 2.38
- Performance
- Read 1.4-1.9
- Practice Examples; 1.5–7; 2.39-40
- HW11 performance (due Fri Oct 18)
23: Thu Oct 17 6
- Lab6 Single-Cycle Processor II (due Thu Oct 24)
- CATME single cycle team eval (due Mon Oct 21)
- Due: * HW12
- Due: * HW13
- Due: * Lab5
- Due: * HW10
24: Fri Oct 18 6
- Quiz 3
- Due: * HW11
25: Mon Oct 21 7
- Pipelined datapath and control
- Read 4.6-4.7
- Practice 4.19-20
- CATME pipeline team forming survey (due Tue Oct 22)
- Due: * CATME single cycle team eval
26: Tue Oct 22 7
- More Pipelined datapath and control
- Due: * CATME pipeline team forming survey
27: Thu Oct 24 7
- Data and control hazards
- Read 4.8-4.9
- Practice 4.22; 4.26
- HW15 pipelined instructions (due Tue Oct 29)
- Due: * Lab6
28: Fri Oct 25 7
- Lab7 Pipelined Processor I (due Thu Oct 31)
29: Mon Oct 28 8
- More hazards
30: Tue Oct 29 8
- Adding pipelined instructions
- Due: * HW15
31: Thu Oct 31 8
32: Fri Nov 01 8
- Quiz 4
33: Mon Nov 04 9
- Branching with a Pipelined Processor
34: Tue Nov 05 9
- Pipelined Performance
35: Thu Nov 07 9
- Adding more pipelined instructions
- Due: * Lab8
36: Fri Nov 08 9
- Lab9 Pipelined Processor III (due Thu Nov 14)
37: Mon Nov 11 10
- Other Architectures II
- x86 insts
38: Tue Nov 12 10
- Lab 10: Pipelined Processor IV (design)
- CATME single cycle team eval (due Fri Nov 15)
39: Thu Nov 14 10
- Quiz 5
- Due: * Lab9
40: Fri Nov 15 10
- Wrap up (attendance required)
- Due: * CATME single cycle team eval