CSSE232 : Computer Architecture I

Name: Date:

HW9

Consider the verilog code for the module THING described below.
```
module THING(
    input wire [3:0] din,
    output wire [3:0] dout
)

always @(din) begin
    dout = din + 1;
end
endmodule
```
a. (4 points) This module will not compile, it gives an error that says something like 'Illegal reference to net "dout"'. Explain why this error happens and how to fix it.

b. (4 points) This module has very simple behavior, we could use an assign statement to implement the same behavior as the always block. Write the equivalent assign statement.

c. (4 points) If we used the assign statement you built in question b and made no other changes to the starting code would the compilation error from question a still happen? Explain.

(7 points) a. Fill in the definition of the module below. This module stores a number which starts out at 0, and outputs it constantly. At the negative edge of the clock it increments the stored number.
```
 module Incrementor(
     input wire CLK,
     output reg [31:0] dout
 );
```
b . (3 points) Explain why we can't simply use an assign statement to drive the output in a clocked module, like this one.