1: Mon Dec 02 1

• Introduction
  • Read Ch 1 (esp. 1.1–1.3, 1.10)
• Course Overview
  • Read B.2, B.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
  • Practice B.11; 2.8
• Lab0 Course tools (due Wed Dec 04)
• HW1 (due Wed Dec 04)

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2: Tue Dec 03 1

• MIPS green sheet
• Intro to MIPS assembly
  • Read 2.1–2.3
  • Practice 2.1–2.6; 2.9–2.10
• Representing instructions
  • Read 2.4–2.5
  • Practice 2.12; 2.14–2.18
• HW2 (due Thu Dec 05)

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3: Wed Dec 04 1

• Lab1 (due Fri Dec 06)
  • Skim A.9–A.10
• Due: * Lab0 Course tools
• Due: * HW1

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4: Thu Dec 05 1

• Logical operations
  • Read 2.6
  • Practice 2.19–20,22
• Decision instructions
  • Read 2.7
  • Practice 2.23–24; 2.26; 2.29–30
• HW3 (due Mon Dec 09)
• Due: * HW2

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5: Fri Dec 06 1

• Lab2 (due Tue Dec 10)
• HW4 (due Tue Dec 10)
• Due: * Lab1

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6: Mon Dec 09 2

• Performance
  • Read 1.4–1.9
  • Practice Examples; 1.5–7
• HW5 (due Wed Dec 11)
• Due: * HW3

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7: Tue Dec 10 2

• Procedures
  • Read 2.8; A.6
  • Practice 2.31; 2.33-34; 2.36
• HW6 (due Thu Dec 12)
• Due: * Lab2
• Due: * HW4

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8: Wed Dec 11 2

• Lab3 (due Fri Dec 13)
• Due: * HW5

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9: Thu Dec 12 2

• More procedures
  • Read 2.13
  • Practice 2.31; 2.33-34; 2.36
• HW7 (due Mon Dec 16)
• Due: * HW6

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10: Fri Dec 13 2

• Lab4 (due Tue Dec 17)
• Due: * Lab3

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11: Mon Dec 16 3

• Addressing modes
  • Read 2.10
  • Practice 2.39–42
• HW8 (due Wed Dec 18)
• Due: * HW7

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12: Tue Dec 17 3

• Other architectures
• HW9 (due Thu Dec 19)
• Due: * Lab4

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13: Wed Dec 18 3

• Performance review continued
• Exceptions
  • Read A.7–8
  • Practice A.3–5
• I/O
  • Read 2.9
  • Practice 2.38
• Lab5 (due Fri Dec 20)
• HW10 (due Fri Dec 20)
• Due: * HW8

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14: Thu Dec 19 3

• Running a program
  • Read 2.12,14,15; A.1–5
• Due: * HW9

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15: Fri Dec 20 3

• Project overview
• Continue Lab5
• M0 (due Tue Jan 07)
• Due: * Lab5
• Due: * HW10

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Break

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16: Mon Jan 06 4

• Building a datapath
  • Read 4.1–3
  • Practice 4.1–4

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17: Tue Jan 07 4

• Review for exam 1
• Example Exam 1 and solution
• Due: * M0

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18: Wed Jan 08 4

• Exam 1

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19: Thu Jan 09 4

• A simple implementation scheme
• Read 4.4
• Practice 4.6–7
• Single cycle datapath and control
  • Read Single-cycle RTL

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20: Fri Jan 10 4

• Multicycle datapath
  • Read Multicycle rtl
  • Read Multicycle datapath
  • M1 (due Wed Jan 15)

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21: Mon Jan 13 5

• Multicycle control
  • Read Multicycle control

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22: Tue Jan 14 5

• Review exam
• HW11 (due Fri Jan 17)

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23: Wed Jan 15 5

• More multicycle details
• Pipelined datapath and control
  • Read 4.5–4.6
  • Practice 4.8-4.9
• HW12 (due Mon Jan 20)
• Due: * M1

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24: Thu Jan 16 5

• Group meetings
• M2 (due Wed Jan 22)

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25: Fri Jan 17 5

• Group meetings
• Due: * HW11

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26: Mon Jan 20 6

• Xilinx survival guide
• Mux2_2 files
• HW13 (due Fri Jan 24)
• Lab6 (due Fri Jan 31)
• Lab7 (due Fri Jan 31)
• Lab8 (due Fri Jan 31)
• Due: * HW12

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27: Tue Jan 21 6

• Data and control hazards
  • Read 4.7–4.8
  • Practice 4.10; 4.12–14

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28: Wed Jan 22 6

• More hazards
• Adding pipelined instructions
• Pipelined exceptions
  • Read 4.9
  • Practice 4.17
• Multicycle exceptions
• HW14 (due Tue Jan 28)
• M3 (due Wed Jan 29)
• Due: * M2

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29: Thu Jan 23 6

• Group meetings

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30: Fri Jan 24 6

• Group meetings
• Due: * HW13

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31: Mon Jan 27 7

• Project time

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32: Tue Jan 28 7

• More Xilinx and Verilog
• Due: * HW14

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33: Wed Jan 29 7

• Project time
• Due: * M3

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34: Thu Jan 30 7

• Group meetings
• M4 (due Wed Feb 05)

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35: Fri Jan 31 7

• Group meetings
• Due: * Lab6
• Due: * Lab7
• Due: * Lab8

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36: Mon Feb 03 8

• Project time

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37: Tue Feb 04 8

• Exam review
• Example Exam 2 and partial solution

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38: Wed Feb 05 8

• Exam 2
• Due: * M4

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39: Thu Feb 06 8

• Group meetings
• M5 (due Wed Feb 12)

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40: Fri Feb 07 8

• Group meetings

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41: Mon Feb 10 9

• Project time

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42: Tue Feb 11 9

• Project time

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43: Wed Feb 12 9

• Exam review
• Wrap up
• Due: * M5

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44: Thu Feb 13 9

• Group meetings
• M6 (due Wed Feb 19)

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45: Fri Feb 14 9

• Group meetings

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