CSSE232 : Computer Architecture I

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1: Thu Sep 05 1

Introduction
- Read Ch 1 (esp. 1.1-1.3, 1.11)
Course Overview
- Read A.2, A.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
- Practice A.11; 2.6
HW1 review (due Mon Sep 09)
Note: HWs are always due at class time. There is one shared gradescope for all sections, so the due time on gradescope may not reflect the correct time for all sections.

2: Fri Sep 06 1

RISC-V green sheet
Intro to RISC-V assembly
- Read 2.1-2.3
- Practice 2.1-2.4; 2.7-2.8
RISC-V R-types
- Arithmetic operations
- Logical operations
- Read 2.6
- Practice 2.17-18,20
HW2 compiling c into assembly (due Tue Sep 10)

3: Mon Sep 09 1

RISC-V I-types
- Read 2.10 (Important reading)
HW3 assembling instructions (due Thu Sep 12)
Due: * HW1

4: Tue Sep 10 1

Practical1 Assembler I (due Mon Sep 16)
Due: * HW2

5: Thu Sep 12 2

RISC-V Branches and Jumps
- Read 2.7
- Practice 2.21-22; 2.24; 2.27-28
HW4 loops (due Mon Sep 16)
Due: * HW3

6: Fri Sep 13 2

Pseudoinstructions
- Read 2.12 "Assembler" section
HW5 pseudoinstructions (due Tue Sep 17)

7: Mon Sep 16 2

Practical2 Assembler II (due Mon Sep 23)
Due: * Practical1
Due: * HW4

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8: Tue Sep 17 2

Quiz 1
Due: * HW5

9: Thu Sep 19 3

Addressing modes
- Read 2.10 (Important reading)
- Practice 2.12; 2.22
- Immediate Translation Handout
HW6 addressing modes (due Mon Sep 23)

10: Fri Sep 20 3

Procedures
- Read 2.8; (this is an important reading)
- Practice 2.29-31; 2.33
HW7 procedure calling (due Tue Sep 24)

11: Mon Sep 23 3

More procedures
- Read 2.13
HW8 procedures and loops (due Thu Sep 26)
Due: * Practical2
Due: * HW6

12: Tue Sep 24 3

Practical3 RISC-V Programming (due Mon Sep 30)
Due: * HW7

13: Thu Sep 26 4

Verilog survival guide 1
- Video
Verilog survival guide 2
- Video
HW9 write verilog code (due Mon Sep 30)
Due: * HW8

14: Fri Sep 27 4

Building a datapath (R-types)
- Read 4.1-3
- Practice 4.1-4
HW10 write relprime (due Fri Oct 04)

15: Mon Sep 30 4

Practical4 Building and Testing Hardware (due Mon Oct 07)
Due: * Practical3
Due: * HW9

16: Tue Oct 01 4

Quiz 2

17: Thu Oct 03 5

Building a datapath (I-types and memory)
Single cycle datapath and control
- Read Single-cycle RTL
CATME singlecycle team forming survey (due Fri Oct 04)

18: Fri Oct 04 5

More Single-Cycle (Branches and Jumps)
HW11 add single cycle instruction (due Tue Oct 15)
Due: * HW10
Due: * CATME singlecycle team forming survey

19: Mon Oct 07 5

Single-Cycle Control
- Read 4.4
- Practice 4.4-5
HW12 single cycle control (due Thu Oct 17)
Due: * Practical4

20: Tue Oct 08 5

Practical5 Single-Cycle Processor I (due Thu Oct 17)

21: Mon Oct 14 6

Other architectures
- Read 2.16-19
HW13 various architectures (due Thu Oct 17)

22: Tue Oct 15 6

I/O
- Read 2.9
- Practice 2.38
Performance
- Read 1.4-1.9
- Practice Examples; 1.5–7; 2.39-40
HW14 performance (due Fri Oct 18)
Due: * HW11

23: Thu Oct 17 6

Practical6 Single-Cycle Processor II (due Thu Oct 24)
CATME single cycle team eval (due Mon Oct 21)
Due: * HW12
Due: * Practical5
Due: * HW13

24: Fri Oct 18 6

Quiz 3
Due: * HW14

25: Mon Oct 21 7

Pipelined datapath and control
- Read 4.6-4.7
- Practice 4.19-20
CATME pipeline team forming survey (due Tue Oct 22)
Due: * CATME single cycle team eval

26: Tue Oct 22 7

More Pipelined datapath and control
Due: * CATME pipeline team forming survey

27: Thu Oct 24 7

Data and control hazards
- Read 4.8-4.9
- Practice 4.22; 4.26
Due: * Practical6

28: Fri Oct 25 7

Practical7 Pipelined Processor I (due Thu Oct 31)

29: Mon Oct 28 8

More hazards
HW15 pipeline diagrams and efficiency (due Fri Nov 01)

30: Tue Oct 29 8

Adding pipelined instructions
HW16 add inst to pipeline (due Fri Nov 01)

31: Thu Oct 31 8

Practical8 Pipelined Processor II (due Thu Nov 07)
Due: * Practical7

32: Fri Nov 01 8

Quiz 4
Due: * HW15
Due: * HW16

33: Mon Nov 04 9

Branching with a Pipelined Processor

34: Tue Nov 05 9

Pipelined Performance
HW17 pipelined branch performance (due Fri Nov 08)

35: Thu Nov 07 9

Adding more pipelined instructions
Due: * Practical8

36: Fri Nov 08 9

Practical9 Pipelined Processor III (due Thu Nov 14)
Due: * HW17

37: Mon Nov 11 10

Other Architectures II
- x86 insts

38: Tue Nov 12 10

Practical 10: Pipelined Processor IV (design)
CATME single cycle team eval (due Fri Nov 15)

39: Thu Nov 14 10

Quiz 5
Due: * Practical9

40: Fri Nov 15 10

Wrap up (attendance required)
Due: * CATME single cycle team eval