1: Mon Nov 29 1

• Introduction
  • Read Ch 1 (esp. 1.1-1.3, 1.11)
• Course Overview
  • Read B.2, B.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
  • Practice B.11; 2.6
• HW1 (due Wed Dec 01)

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2: Tue Nov 30 1

• MIPS green sheet
• Intro to MIPS assembly
  • Read 2.1-2.3
  • Practice 2.1-2.4; 2.7-2.8
• Representing instructions
  • Read 2.4-2.5
  • Practice 2.10; 2.12-2.16
• HW2 (due Thu Dec 02)

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3: Wed Dec 01 1

• Logical operations

  • Read 2.6
  • Practice 2.17-18,20

• Lab1 (due Fri Dec 03)

  • Skim A.9-A.10

• HW3 (due Fri Dec 03)

• Due: * HW1

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4: Thu Dec 02 1

• Decision instructions
  • Read 2.7
  • Practice 2.21-22; 2.24; 2.27-28
• HW4 (due Mon Dec 06)
• Due: * HW2

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5: Fri Dec 03 1

• Procedures

  • Read 2.8; A.6 (this is an important reading)
  • Practice 2.29-31; 2.33

• Due to edits in the schedule HW6 is coming before HW5 this quarter -- dont worry about it

  • HW6 (due Tue Dec 07)

• Due: * Lab1

• Due: * HW3

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6: Mon Dec 06 2

• Lab2 (due Wed Dec 08)
• HW5 (due Fri Dec 10)
• Due: * HW4

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7: Tue Dec 07 2

• More procedures
  • Read 2.13
  • Practice see previous procedures day
• HW7 (due Thu Dec 09)
• Due: * HW6

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8: Wed Dec 08 2

• Addressing modes
  • Read 2.10 (Important reading)
  • Practice 2.12; 2.22
• Lab3 (due Fri Dec 10)
• HW8 (due Fri Dec 10)
• Due: * Lab2

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9: Thu Dec 09 2

• Performance
  • Read 1.4-1.9
  • Practice Examples; 1.5–7; 2.39-40
• HW9 (due Mon Dec 13)
• Due: * HW7

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10: Fri Dec 10 2

• Performance review continued
• Exceptions
  • Read A.7-8
  • Practice A.3-5
• HW10 (due Mon Dec 13)
• Due: * HW5
• Due: * Lab3
• Due: * HW8

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11: Mon Dec 13 3

• Review for exam 1
• Example Exam 1 and solution
• Due: * HW9
• Due: * HW10

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12: Tue Dec 14 3

• Other architectures
  • Read 2.16-19
• HW11 (due Mon Jan 03)

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13: Wed Dec 15 3

• Exam 1

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14: Thu Dec 16 3

• Project overview
• Lab0 Course tools (due Thu Jan 06)
• CATME Team Survey (due Fri Dec 17)

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15: Fri Dec 17 3

• Running a program

  • Read 2.12,14,15; A.1-5

• Due: * CATME Team Survey

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Break

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16: Mon Jan 03 4

• Xilinx survival guide 1
• Mux2_2 files
• M1 (due Wed Jan 12)
• Due: * HW11

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17: Tue Jan 04 4

• Xilinx survival guide 2

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18: Wed Jan 05 4

• Exam 1 Redo opportunity
• Lab4 (due Fri Jan 07)

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19: Thu Jan 06 4

• Building a datapath

  • Read 4.1-3
  • Practice 4.1-4

• Due: * Lab0 Course tools

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20: Fri Jan 07 4

• A simple implementation scheme
• Read 4.4
• Practice 4.4-5
• Single cycle datapath and control
  • Read Single-cycle RTL
• HW12 (due Tue Jan 11)
• Due: * Lab4

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21: Mon Jan 10 5

• Multicycle datapath
  • Read 4.5 pages 1-12 From the online materials of the textbook, here.
  • Read Multicycle rtl
  • Read Multicycle datapath
• Lab7 (due Fri Jan 21)
• Note this is a TEAM lab and we don't have time in-class allocated specifically for this lab

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22: Tue Jan 11 5

• Multicycle control
  • Read 4.5 pages 13-22 (from the online materials)
  • Read Multicycle control
• HW13 (due Fri Jan 14)
• Due: * HW12

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23: Wed Jan 12 5

• More multicycle details
• I/O
  • Read 2.9
  • Practice 2.38
• M2 (due Wed Jan 19)
• Project Worktime
• Due: * M1

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24: Thu Jan 13 5

• M1 Group meetings

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25: Fri Jan 14 5

• M1 Group meetings
• Due: * HW13

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26: Mon Jan 17 6

• Pipelined datapath and control
  • Read 4.6-4.7
  • Practice 4.19-20
• HW14 (due Fri Jan 21)

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27: Tue Jan 18 6

• Data and control hazards
  • Read 4.8-4.9
  • Practice 4.22; 4.26
• HW15 (due Mon Jan 24)

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