CSSE232 : Computer Architecture I

1: Thu Sep 05

  • Introduction
    • Read Ch 1 (esp. 1.1–1.3, 1.10)
  • Course Overview
    • Read B.2, B.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
    • Practice B.11; 2.8
  • Lab0 Course tools (due Mon Sep 09)
  • HW1 (due Mon Sep 09)

2: Fri Sep 06

  • MIPS green sheet
  • Intro to MIPS assembly
    • Read 2.1–2.3
    • Practice 2.1–2.6; 2.9–2.10
  • Representing instructions
    • Read 2.4–2.5
    • Practice 2.12; 2.14–2.18
  • HW2 (due Tue Sep 10)

3: Mon Sep 09


4: Tue Sep 10

  • Logical operations
    • Read 2.6
    • Practice 2.19–20,22
  • Decision instructions
    • Read 2.7
    • Practice 2.23–24; 2.26; 2.29–30
  • HW4 (due Thu Sep 12)
  • Due: * HW2

5: Wed Sep 11

  • Lab2 (due Fri Sep 13)
  • HW5 (due Fri Sep 13)
  • Due: * Lab1


6: Thu Sep 12


7: Fri Sep 13

  • Procedures
    • Read 2.8; A.6
    • Practice 2.31; 2.33-34; 2.36
  • HW7 (due Tue Sep 17)
  • Due: * Lab2
  • Due: * HW5

8: Mon Sep 16


9: Tue Sep 17

  • More procedures
    • Read 2.13
    • Practice 2.31; 2.33-34; 2.36
  • HW9 (due Thu Sep 19)
  • Due: * HW7

10: Wed Sep 18



11: Thu Sep 19

  • Addressing modes
    • Read 2.10
    • Practice 2.39–42
  • HW11 (due Mon Sep 23)
  • Due: * HW9

12: Fri Sep 20

  • Other architectures
  • HW12 (due Tue Sep 24)
  • Due: * Lab4

13: Mon Sep 23

  • Performance review continued
  • Exceptions
    • Read A.7–8
    • Practice A.3–5
  • I/O
    • Read 2.9
    • Practice 2.38
  • Lab5 (due Fri Sep 27)
  • HW13 (due Wed Sep 25)
  • Due: * HW11

14: Tue Sep 24


15: Wed Sep 25

  • Exam 1
  • M0 (due Fri Sep 27)
  • Due: * HW13


16: Thu Sep 26


17: Fri Sep 27

  • Running a program
    • Read 2.12,14,15; A.1–5
  • Due: * Lab5
  • Due: * M0

18: Mon Sep 30

  • Building a datapath
    • Read 4.1–3
    • Practice 4.1–4

19: Tue Oct 01

  • A simple implementation scheme
  • Read 4.4
  • Practice 4.6–7
  • Single cycle datapath and control

20: Wed Oct 02



21: Thu Oct 03


22: Fri Oct 04

  • Project time
  • HW22 (due Wed Oct 09)

23: Mon Oct 07

  • More multicycle details
  • Pipelined datapath
    • Read 4.5–4.6
    • Practice 4.8
  • HW23 (due Mon Oct 14)
  • M2 (due Tue Oct 15)

24: Tue Oct 08

  • Pipelined datapath and control
    • Read 4.6
    • Practice 4.9
  • Due: * M1

25: Wed Oct 09

  • Group meetings
  • Due: * HW22


26: Mon Oct 14


27: Tue Oct 15

  • Data and control hazards
    • Read 4.7–4.8
    • Practice 4.10; 4.12–14
  • Due: * M2

28: Wed Oct 16

  • More hazards
  • Adding pipelined instructions
  • Pipelined exceptions
    • Read 4.9
    • Practice 4.17
  • Multicycle exceptions
  • HW30 (due Tue Oct 22)
  • M3 (due Wed Oct 23)

29: Thu Oct 17

  • Group meetings

30: Fri Oct 18

  • Group meetings
  • Due: * HW28


31: Mon Oct 21

  • Project time

32: Tue Oct 22

  • More Xilinx and Verilog
  • Due: * HW30

33: Wed Oct 23

  • Project time
  • Due: * M3

34: Thu Oct 24

  • Group meetings
  • M4 (due Wed Oct 30)

35: Fri Oct 25



36: Mon Oct 28

  • Project time

37: Tue Oct 29


38: Wed Oct 30

  • Exam 2
  • Due: * M4

39: Thu Oct 31

  • Group meetings
  • M5 (due Wed Nov 06)

40: Fri Nov 01

  • Group meetings


41: Mon Nov 04

  • Project time

42: Tue Nov 05

  • Project time

43: Wed Nov 06

  • Exam review
  • Wrap up
  • Due: * M5

44: Thu Nov 07

  • Group meetings
  • M6 (due Wed Nov 13)

45: Fri Nov 08

  • Group meetings


46: Mon Nov 11

  • Project time

47: Tue Nov 12


48: Wed Nov 13


49: Thu Nov 14


50: Fri Nov 15