CSSE232 : Computer Architecture I

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1: Thu Sep 03 1

Introduction
- Read Ch 1 (esp. 1.1–1.3, 1.10)
Course Overview
- Read B.2, B.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
- Practice B.11; 2.8
HW1 (due Mon Sep 07)

2: Fri Sep 04 1

MIPS green sheet
Intro to MIPS assembly
- Read 2.1–2.3
- Practice 2.1–2.6; 2.9–2.10
Representing instructions
- Read 2.4–2.5
- Practice 2.12; 2.14–2.18
HW2 (due Tue Sep 08)

3: Mon Sep 07 1

Lab1 (due Wed Sep 09)
- Skim A.9–A.10
Due: * HW1

4: Tue Sep 08 1

Logical operations
- Read 2.6
- Practice 2.19–20,22
Decision instructions
- Read 2.7
- Practice 2.23–24; 2.26; 2.29–30
HW3 (due Thu Sep 10)
Due: * HW2

5: Wed Sep 09 1

Lab2 (due Fri Sep 11)
HW4 (due Fri Sep 11)
Due: * Lab1

6: Thu Sep 10 2

Procedures
- Read 2.8; A.6
- Practice 2.31; 2.33-34; 2.36
HW5 (due Mon Sep 14)
Due: * HW3

7: Fri Sep 11 2

More procedures
- Read 2.13
- Practice 2.31; 2.33-34; 2.36
HW6 (due Tue Sep 15)
Due: * Lab2
Due: * HW4

8: Mon Sep 14 2

Performance
- Read 1.4–1.9
- Practice Examples; 1.5–7
HW7 (due Wed Sep 16)

9: Tue Sep 15 2

Addressing modes
- Read 2.10
- Practice 2.39–42
Due: * HW6

10: Wed Sep 16 2

Lab3 (due Fri Sep 18)
Lab4 (due Fri Sep 18)
Due: * HW7

11: Thu Sep 17 3

Performance review continued
Exceptions
- Read A.7–8
- Practice A.3–5
HW8 (due Mon Sep 21)

12: Fri Sep 18 3

Other architectures
HW10 (due Tue Sep 22)
Due: * Lab3
Due: * Lab4

13: Mon Sep 21 3

Lab5 (due Wed Sep 23)
Due: * HW8

14: Tue Sep 22 3

Review for exam 1
Example Exam 1 and solution
Due: * HW10

15: Wed Sep 23 3

Exam 1
Due: * Lab5

16: Thu Sep 24 4

Project overview
Team Survey (due Mon Sep 28)

17: Fri Sep 25 4

Running a program
- Read 2.12,14,15; A.1–5

18: Mon Sep 28 4

Building a datapath
- Read 4.1–3
- Practice 4.1–4
Due: * Team Survey

19: Tue Sep 29 4

A simple implementation scheme
Read 4.4
Practice 4.6–7
Single cycle datapath and control
- Read Single-cycle RTL

20: Wed Sep 30 4

Review exam
HW11 (due Mon Oct 05)

21: Thu Oct 01 5

Multicycle datapath
- Read Multicycle rtl
- Read Multicycle datapath
- M1 (due Tue Oct 06)

22: Fri Oct 02 5

Multicycle control
- Read Multicycle control

23: Mon Oct 05 5

Project Worktime
Due: * HW11

24: Tue Oct 06 5

More multicycle details
Pipelined datapath and control
- Read 4.5–4.6
- Practice 4.8-4.9
HW12 (due Tue Oct 13)
Due: * M1

25: Wed Oct 07 5

Group meetings
M2 (due Thu Oct 15)

Break

26: Mon Oct 12 6

Xilinx survival guide
Mux2_2 files
HW13 (due Fri Oct 16)
Lab6 (due Fri Oct 23)
Lab7 (due Fri Oct 23)

27: Tue Oct 13 6

Data and control hazards
- Read 4.7–4.8
- Practice 4.10; 4.12–14
Due: * HW12

28: Wed Oct 14 6

More hazards
Adding pipelined instructions
Pipelined exceptions
- Read 4.9
- Practice 4.17
Multicycle exceptions
HW14 (due Tue Oct 20)
M3 (due Wed Oct 21)

29: Thu Oct 15 6

Group meetings
Due: * M2

30: Fri Oct 16 6

Group meetings
Due: * HW13

31: Mon Oct 19 7

Project time

32: Tue Oct 20 7

More Xilinx and Verilog
Due: * HW14

33: Wed Oct 21 7

Project time
Content Quiz 10 - Pipelining
Due: * M3

34: Thu Oct 22 7

Group meetings
M4 (due Wed Oct 28)

35: Fri Oct 23 7

Group meetings
Due: * Lab6
Due: * Lab7

36: Mon Oct 26 8

Project time

37: Tue Oct 27 8

Exam review
Example Exam 2 and partial solution

38: Wed Oct 28 8

Exam 2
Due: * M4

39: Thu Oct 29 8

Group meetings
M5 (due Wed Nov 04)

40: Fri Oct 30 8

Group meetings

41: Mon Nov 02 9

Project time

42: Tue Nov 03 9

Project time

43: Wed Nov 04 9

Wrap up (Zoom attendance required)
Due: * M5

44: Thu Nov 05 9

Group meetings
M6 (due Wed Nov 11)

45: Fri Nov 06 9

Group meetings

46: Mon Nov 09 10

Project time

47: Tue Nov 10 10

Project time

48: Wed Nov 11 10

Project time
Due: * M6

49: Thu Nov 12 10

Group meetings
Final presentation (due on final day)
Final report (due on final day)
Group eval (due on final day)

50: Fri Nov 13 10

Group meetings