CSSE232 : Computer Architecture I

Name: Date:

HW2 solution

(20 points) Convert the following C code to RISC-V assembly instructions. Use the minimum number of instructions necessary. Assume that variables f, g and h are 32- bit integers stored in registers x5, x6 and x7 respectively.

Be careful not to modify the initial variable values unintentionally. If you need to store temporary values, use one of the other registers.

a. f = g + h;

add x5, x6, x7

b. f = g - (h - 5);
```
addi x5, x7, -5
sub  x5, x6, x5
```
c. f = 0x12345000 Hint: you cannot achieve this with a singular addi instruction, get creative with multiple instructions or review the reference sheet.
```
NOTE: because we may not have covered `lui` yet in class, this one was hard!  There are a few ways to do this, here are two:
lui  x5, 0x12345
```
or
```
addi  x5, x0, 0x123   //0x00000123
slli  x5, x5, 8       //0x00012300
addi  x5, x0, 0x45    //0x00012345
slli  x5, x5, 12      //0x12345000
```
d. g = 0x11111111 Hint: you cannot achieve this with a singular addi instruction, get creative with multiple instructions or review the reference sheet.
```
NOTE: because we may not have covered `lui` yet in class, this one was hard!  There are a few ways to do this, here are two:
lui  x6, 0x11111
addi x6, x6, 0x111
```
or
```
addi  x6, x0, 0x111   //0x00000111
slli  x6, x6, 12      //0x00111000
addi  x6, x6, 0x111   //0x00111111
slli  x6, x6, 8       //0x11111100
addi  x6, x6, 0x11    //0x11111111
```
e. h = 0x00000FFF Be careful with how RISC-V sign extends immediates!

NOTE: this one is tricky because of sign extension. There are a few ways to do this, here are two:
```
lui  x7, 1
addi x7, x7, -1
```
or
```
addi x7, x0, -1   // 0xFFFFFFFF
srli x7, x7, 20   // shifts right 20 bits with zero-extension
```

(Continues on next page)

(5 points) Consider changing the RISC-V instruction set to support 64 registers instead of 32. Draw the new R-type instruction format. You may not change the size of the opcode, funct3, nor funct7; you may only make changes to the register fields. You may go beyond 32 bits if necessary. Be sure to label each field and include its size.

f7 rs2 rs1 f3 rd op

7 6 6 3 6 7

Total size of 35 bits. Padding 5 bits to have a total of 40 bits to be byte-aligned is also acceptable.
(5 points) How many possible R-type instructions does RISC-V support if every possible combination of opcode, funct7, and funct3 are valid instructions? (You can ignore other instruction types for this question.)

There are $2^{7}$ possible opcodes. $2^{7}$ possible funct7's, and $2^{3}$ possible funct3's. So in total there are:
$$ |inst| = 2^{7} * 2^{3} * 2^{7} = 2^{17} = 131,072$$