CSSE232 : Computer Architecture I

Name: Date:

HW14

You are the lead designer of a processor and wish to evaluate design options and pick the most efficient. For all problems show your work and include units in your calculations for full credit.

(3 points) Base design You first analyze the current design, Mbase, which has a clock rate of 2.5 GHz. (Note that Hz = cycles/second, track your units carefully.) Testing with a benchmark program yields the measurements below. What is the execution time of this porgram.

Instruction Class CPI Count

R 1 40

I 1 25

Mem 1 25

SB/J 1 10
Your team is going to add the l_inc instruction (from HW11) to your processor.

a. (2 points) What effect is this likely to have on the cycle time if you implement this on Mbase? Justify your answer by explaining how the critical path changes or do not change with the addition of this instruction.

b. (3 points) You are now required to use a new set of hardware components with the following execution times: Memory - 2ns, ALU - 2ns, registers - 1ns, others - 0ns. Estimate the new cycle time for l_inc.
Your team is going to add the add4_mem instruction, which does the following: rd = Mem[rs1+imm] + 4

a. (2 points) What effect is this likely to have on the cycle time if you implement this on Mbase? Justify your answer by explaining how the critical path changes or do not change with the addition of this instruction.

b. (3 points) You are now required to use a new set of hardware components with the following execution times: Memory - 2ns, ALU - 2ns, registers - 1ns, others - 0ns. Estimate the new cycle timefor add4_mem.

Instruction Class	CPI	Count
R	1	40
I	1	25
Mem	1	25
SB/J	1	10

Your team creates two new compilers, each one uses one of the new instructions described above. C1 incorporates the lw_inc instruction, while C2 incorporates the add4_mem instruction. Both runs on the new hardware components as described in the part b of the previous two questions.

a. (6 points) Estimate the execution time for the compiled program on each of the modified processor designs you discuss above.

Instruction Class CPI C1 Instr Count C2 Instr Count

R 1 30 35

I 1 25 20

Mem 1 25 20

SB/J 1 10 10

b. (3 points) You realize that your team can only implement one of these two new instructions. Which one should your team implement? Or should they stick with the base RISC-V design? Justify your answer.