CSSE 232 Computer Architecture I |
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| Handouts | |
| R-00 | Project Resources |
| R-01 | Exam 1 from Winter 2003-2004 Solutions |
| R-02 | Exam 2 from Fall 2003-2004 Solutions |
| R-03 | Xilinx Tutorial 1 (Using the Project Navigator, Schematic tool, HDL Bencher, ModelSim and CoreGen) |
| R-04 | Xilinx Tutorial 2 (Creating hierarchical schematics) |
| R-05 | ALU Diagram from Exam 1 |
| R-06 | Xilinx Tutorial 3 (StateCad) |
| R-07 | RTL descriptions for some MIPS instructions (Multi-cycle) |
| R-08 | Xilinx Tutorial 4 (Simulating Verilog) Sample Verilog files Verilog Intro |
| R-09 | Xilinx Tutorial 5 (Measuring delay and size) ALU_test.zip |
| R-10 |
Memory module (2 segments: 1
for the program, 1 for the Interrupt Service Routines) Memory module (3 segments: the above and a segment for the stack). Sample register file |
| R-11 | Exam 2 from Winter 2003-2004 Solutions |
| R-12 | Restoring division algorithm (The enhanced version) |
| R-13 | |
| R-14 | |
| R-15 | |
| R-16 | |
| R-17 | |
| R-18 | |
| R-19 |
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Last modified: Tuesday November 02, 2004 |