Schedule Mohammad's Schedule Syllabus Resources Moodle Gradescope

Name: Date:

CSSE232 Practical 1 Worksheet

Read and perform the practical guide posted on the course website. Answer the questions in the practical guide. Numbers in square brackets (e.g. []) indicate the point value of each question. The annotations in parentheses refer to the list of "general practical requirements" from the practical page. The answers to these questions should be as concise as possible. Maintain the spacing provided by this template.

• [8] (Need) Explain what an assembler is needed for.

• [8] (Performance) Is this assembler implemented in Python the best performing assembler? What are factors impacting the performance of assemblers? Discuss at least two of these factors.

• [8] (Correctness) How do you know your assembler works? What instructions have you chosen to include in your test program? Do not simply answer “the output machine code is correct,” you must explain why your chosen set of instructions in your test programs give you the confidence that you have a valid working assembler.

• [8] (Iteration) Explain how your instructor can see your iterative approach to implementing the assembler. For example you can point to several git commits that show changes over time and contain messages explaining the changes.

• [8] (Correctness) I asked ChatGPT the following prompt: “Do all RISC-V instruction formats have a unique opcode?” GPT responded:

    “No, not all RISC-V instruction formats have a unique opcode. The opcode
    field in RISC-V is not unique to a specific instruction format… Instead,
    multiple instruction formats may share the same opcode but are
    distinguished by other fields (such as funct3, funct7, and others) to
    differentiate between specific operations… In RISC-V, the opcode is a 7-bit
    field located at the least significant bits (LSBs) of an instruction. These
    7 bits define broad categories of instructions but are shared across
    multiple formats.
  
    Consider these two instructions:
    1.  ADD x10, x11, x12 (R-type)
    2.  ADDI x10, x11, 5 (I-type)
  
    Both instructions have the same opcode (0010011), but the format and meaning differ:
  
    Instruction Opcode  Format  Funct3  Funct7
    ADD         0110011 R-Type  000     0000000
    ADDI        0010011 I-type  000     N/A
  
    The opcode alone does not determine the exact instruction. Additional fields
    (funct3, funct7, etc.) are required to distinguish between them.”

  What did ChatGPT get incorrect in their response? What about RISC-V’s instruction set design makes it tricky to get this detail correct? Reflect upon ChatGPT’s usefulness as a tool to help understand details about RISC-V instruction design

  Full ChatGPT transcript can be found at the end of the worksheet. 

• [8] What was the biggest challenge in implementing the Assembler?

• [10] What is the single biggest thing you learned from writing the assembler? To recieve full credit you must demonstrate meaningful reflection on the assignment.

• [10] Make sure your repository has the three.asm files you created to substantially check your assembler’s validity for variations of R, I, and S types.

• [0] What is the git commit ID for your final commit of your code. This is required to pass the assignment.

Full ChatGPT response

“Do all RISC-V instruction formats have a unique opcode?”

No, not all RISC-V instruction formats have a unique opcode. The opcode field in RISC-V is not unique to a specific instruction format. Instead, multiple instruction formats may share the same opcode but are distinguished by other fields (such as funct3, funct7, and others) to differentiate between specific operations.

📚 Understanding the RISC-V Opcode Field

In RISC-V, the opcode is a 7-bit field located at the least significant bits (LSBs) of an instruction. These 7 bits define broad categories of instructions but are shared across multiple formats.

🧱 Common Instruction Formats in RISC-V

Here are the main RISC-V instruction formats:

• R-type (Register-Register operations)
• I-type (Immediate value operations)
• S-type (Store instructions)
• B-type (Branch instructions)
• U-type (Upper immediate operations)
• J-type (Jump instructions)

🔍 Example of Opcode Sharing Consider these two instructions:

1. ADD x10, x11, x12 (R-type)
2. ADDI x10, x11, 5 (I-type) Both instructions have the same opcode (0010011), but the format and meaning differ:

Instruction	Opcode	Format	Funct3	Funct7
ADD	0110011	R-Type	000	0000000
ADDI	0010011	I-type	000	N/A

The opcode alone does not determine the exact instruction. Additional fields (funct3, funct7, etc.) are required to distinguish between them.

✅ Summary

1. Shared Opcodes: Different formats and instructions can share the same opcode.
2. Differentiation: RISC-V uses other fields like funct3 and funct7 to distinguish between instructions.
3. Efficiency: This sharing allows for a compact encoding while supporting a wide range of instructions.