Lab 7 Building a Pipelined Processor

Objectives

This section is not a list of tasks for you to do. It is a list of skills you will have or things you will know after you complete the lab.

Following completion of this lab you should be able to:

Construct a verilog implementation of a very basic pipelined processor that supports R and I-type RISC-V instructions.
Trace code as it executes through a simulated pipelined processor
Use waveform diagrams to debug a processor implementation
Use verilog test benches and a testing framework to test a processor implementation

Because you will be iteratively adding functionality to one processor module, we strongly recommend that you periodically add and commit your progress to git as a backup.
This is a reasonable quick-reference for verilog: Compact Summary

Follow this sequence of instructions to complete the lab. This lab will all be done in your D-group repository

Trace on the provided DP diagram
Design your pipeline stage registers' contents
- build each, call them IF_ID_Reg, etc. so the instances can be IF_ID or similar.
- For each "thing" in the register, make the output named that thing, and an input should have the same name with an _in suffix. For example:
```
input wire [31:0] inst_in,
output reg [31:0] inst,
```
- Be sure to include the clock as an input.
- In the body of the module, create an always block to copy the inputs to their corresponding outputs.
Create Processor.v that has instances of all your pipeline stage registers
Between the registers, instantiate the components you need
- Register File
- PC
- ALU
- No data memory yet (use DP_Memory.v from lab, but only connect the "A" ports.)
Connect the components to your pipeline stage registers
The Memory cycle will just pass data through from EX_MEM to MEM_WB.
Your WB cycle will refer to the register file in your ID cycle.

TODO: CREATE BASIC R-TYPE MODELSIM TEST FOR THEM

Edit our basic R-type test to use your processor (see comments in test).
New modelsim project
- Add all the .v files
- compile
- run the basic test
Build a waveform to show all your stages.
- add a divider between each stage
HINT: do opcodes.do in the console will add some new "Radix" values that will display opcodes and functs as useful words.
Save your waveform.
Run the tests
Fix any errors.

Do it
Test R-types using tb_Pipe.v
- Edit the pipeline_test_tools.vh file
- Tour of test bench file?

Trace on dp diagram
Add any new traced wires to verilog datapath
Add control (or connect it)
- You'll need an ALUSrc mux
Write tests (here's some assembly. Assemble this with your assembler, then add new task to tb_Pipe.v to use it.
Run tests
On worksheet, explain why this set of instructions is sufficient to test I-types, or how you changed it to be better.

Work ahead (go start Lab 8)

General Requirements for all Labs:

In the worksheet, explain how you satisfy each of these items. Some guidelines:

None of these answers should be more than 100 words.
For item 1, ??
For item 2, explain how the pipelined implementation will be faster than your single-cycle ??
For item 3, describe how you designed the tests for I-type and how you know it's enough
For item 4, ?? documentation of your new test? documents in comments?

For extra points, you could:

Submit your completed Lab Worksheet to gradescope.
Lab code will be submitted to your D git repository as new files and committed modifications to the repo we provided you. You must include your name and your teammates' names in a comment at the top of all files you submit.