Lab0 Xilinx tools

1 Objectives

Upon completion of this lab you should have a properly installed, licensed, and functioning copy of the Xilinx ISE tools.

2 General

These instructions are for installing a fully enabled version of Xilinx ISE 14.7. It is important that you install the correct, fully enabled version. Failure to do so will likely lead to significant difficulty on the final project.

Xilinx ISE works well under linux. We can help you if you are interested in using Xilinx under linux, but given the differences in distro, there may be issues we cannot help you with.

You will be installing the full version of Foundation ISE. We are able to provide it for you thanks to a generous donation from Xilinx of 40 floating licenses.

The files to install Xilinx ISE version 14.7 are cached locally on campus. They should be deleted after the installation and testing process is complete. Downloading the necessary files requires approximately 6 GB of disk space and takes only a few minutes, but can take several hours from off campus. Please plan accordingly.

Once installed, Xilinx ISE and the associated tools will require approximately 17 GB of disk space. Additional disk space is needed during the installation process, as well as for projects developed using the software

3 Installing Xilinx ISE 14.7

The entire installation should take a about an hour.

Step 0: Before you begin the installation

Read the Xilinx ISE 14.7 Release Notes and Installation Guide. This document constitutes your primary guidance for this installation.

Read these notes completely.

Download Xilinx_ISE_DS_Lin_14.7_1015_1.tar or Xilinx_ISE_DS_Win_14.7_1015_1.tar as appropriate from Rose-Hulman's DFS:

Step 1: Installing ISE 14.7

Step 2: Running ISE 14.7

Step 3: After you finish

4 Testing your installation

Lots of good information is contained in the ISE In-Depth Tutorial. In particular, you should familiarize yourself with Chapter 3 Schematic-Based Design, Chapter 4 Behavioral Simulation, Chapter 5 Design Implementation, and Chapter 6 Timing Simulation.

To test your installation, you will synthesize, simulate and implement a simple LCD display driver. The ioBlockPart project implements the LCD driver interface specified in Chapter 5 Character LCD Screen of Spartan-3E Starter Kit Board User Guide.

  1. Download ioBlockPart.zip and unzip in a convenient place.

  2. Start Xilinx ISE 14.7.

  3. Open the ioBlockPart project.

  4. Explore the ioBlockPart project

    1. In the "Hierarchy" section of the "Design" tab, fully expand the sources by clicking on all the plusses.
    2. Double-clicking will open the source in a viewer.
    3. Explore the design of the lcd driver.
  5. Synthesize the ioBlockPart project.

    1. Select io_block.sch in the "Hierarchy" section of the "Design" tab.
    2. In the "Processes" section of the "Design" tab, expand the "Synthesize - XST" entry and double-click it.

    If the synthesis process does not run or you get unexplained errors, select Project> Cleanup Project Files and resynthesize.

  6. Behavioral simulation of the ioBlockPart project.

    Behavioral simulation checks that your design implements the correct behavior. It assumes no gate delay and does not check for timing errors.

    Using ISim integrated into the Xilinx ISE tools.

    1. At the top of the "Design" tab, select the "Simulation" view.
    2. Make sure that the drop-down right under the view selector is set to "Behavioral".
    3. In the "Hierarchy" section of the "Design" tab, double-click on io_block_tb_0.v and examine the test bench.
    4. In the "Processes" section of the "Design" tab, expand the "ISim Simulator" entry, and double-click the "Simulate Behavioral Model" entry.
    5. In the ISim window select View > Zoom > To Full View to show the entire waveform.
    6. Enter 25ms into the time window near the right end of the toolbar and click "run" (the button just to the left of the time window).
    7. When the simulation completes, you should see changes to "lcd_D" starting at about 15ms.
    8. Close ISim.
  7. Implement the ioBlockPart project.

    1. At the top of the "Design" tab, select the "Implementation" view.
    2. Select io_block.sch in the "Hierarchy" section of the "Design" tab.
    3. In the "Processes" section of the "Design" tab, expand the "Implement Design" entry and double-click it.
  8. Timing simulation of the ioBlockPart project.

    Timing simulation is a more accurate simulation of your design which allows timing errors to be discovered, but is slower than a behavioral simulation.

    1. At the top of the "Design" tab, select the "Simulation" view.
    2. Select "Post-Route" in the drop-down right under the view selector.
    3. In the "Hierarchy" section of the "Design" tab, select io_block_tb_0.v.
    4. In the "Processes" section of the "Design" tab, expand the "ISim Simulator" entry, and double-click the "Simulate Post-Place & Route Model" entry.
    5. Enter 25ms into the time window near the right side of the toolbar and click "run".
    6. When the simulation completes, you should see changes to "lcd_D" starting at about 15ms.
    7. Close ISim.
  9. Generate a programming file for the ioBlockPart project.

    1. At the top of the "Design" tab, select the "Implementation" view.
    2. Select io_block.sch in the "Hierarchy" section of the "Design" tab.
    3. In the "Processes" section of the "Design" tab, double-click the "Generate Programming File" entry.
  10. Down load the ioBlockPart project to the Spartan 3E Starter board. Boards are typically available for this lab in the CSSE lab.

    1. Connect the Spartan 3E Starter board to power, connect the usb cable to your laptop, and turn the board on (the switch next to the power connection).

    2. Complete any driver installation required for the new usb device.

      Three usb devices should be recognized: a "Xilinx Embedded Platform USB Firmware Loader" and two "Xilinx USB cables". If your detected device(s) are not recognized by name or show yellow question marks, then the Xilinx tools are not properly installed.

      If the board does not appear to be detected, you can reinstall the driver.

      1. Navigate to: C:\Xilinx\14.7\ISE_DS\common\bin\nt64\
      2. Unplug any Xilinx cables that are plugged into your computer
      3. In the file list, right click on install_drivers.exe and say 'Run as Administrator'
    3. Select io_block.sch in the "Hierarchy" section of the "Design" tab.

    4. In the "Processes" section of the "Design" tab, expand the "Configure Target Device" entry and double-click the "Manage Configuration Project (iMPACT)" entry.

    5. In the "ISE iMPACT" dialog, double-click "Boundary Scan" in the "iMPACT Flows" pane.

    6. Right click in the "Boundary Scan" pane and select "Initialize Chain."

    7. Answer "yes" to assigning configuration files.

    8. Select "io_block.bit" and then click "Open" in the first "Assign New Configuration File" dialog. The .bit file might be in the work directory.

    9. Answer "no" to assigning SPI/BPI files.

    10. Click "Bypass" in the next two "Assign New Configuration File" dialogs.

    11. Click "Ok" in the "Device Programming Properties" dialog.

    12. In the "Boundary Scan" pane, right-click on the xc3s500e, io_block.bit symbol and select "Program..."

    13. You should see a message stating "Program Succeeded".

    14. Push the "North" pushbutton on the Spartan board. The LCD display should clear.

    15. Push the "South" pushbutton on the Spartan board. The LCD should display "842X". The last digit 'X' is controled by the switches in the lower right corner of the FPGA board. Try changing the switches and pushing "South" again. Note: the pushbuttons are not debounced and you may need to push them a couple of times.

  11. Once you've successfully tested your installation, delete the installation files.

5 Modifying a project

  1. Open the top-most design file (io_block.sch). The values displayed on the LCD are controlled by the 16-bit bus connected to the out_D pin on lcd_driver. The signal connected to this bus is constructed from 16 1-bit signals: "V,G,G,G,G,V,G,G,G,G,V,G,...". "V" and "G" are 1-bit signals connected to power (VCC) and ground (GND) and produce a "1" and a "0" respectively. So, the input 1000 0100 0010 produces the value 842 on the LCD. The last digit is connected to the switches on the lower right side of the FPGA board.

    Change the leftmost 3 digits to your favorite 3 digit number (using V and G connections). If your favorite number is 842, use your second favorite. By rearranging the V and G signals, you are connecting the pins of out_D to different nets and thus different 1 and 0 signals.

  2. Simulate your modified design. Note: simulating the the complete operation of displaying digits on the LCD is time consuming. Shorter well chosen simulations are sufficient.

  3. Implement your design, download it to the Spartan board and try it out.

  4. Demonstrate your modified design to your instructor. Have them sign the verification sheet (below).

6 Turning It In

One of the laboratory instructors must verify the appropriate steps by signing on the Instructor Verification line of the instructor verification sheet. When you have completed a step that requires verification, simply demonstrate the step to the TA or instructor. Turn in the completed verification sheet.

Submit the instructor verification sheet in hard copy.

7 More Information

Additional resources can be found at http://www.xilinx.com.