Name: Date:
HW5
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(22 points) As discussed on pages 132–134 (Section 2.12 "Assembler"), pseudoinstructions are not part of the RISC-V instruction set, but often appear in RISC-V programs. For each pseudoinstruction in the following table, produce a minimal sequence of core RISC-V instructions to accomplish the same thing.
You may need to use
x31
for some of the sequences, which the CSSE232-assembler treats as an "assembler temporary" register. In the following tables,BIG
refers to a specific number that requires 32 bits to represent andSMALL
to a number that can fit in 11 bits. You may need to refer to portions of the immediates using indices (e.g. BIG[11:0]). Unless otherwise specified assume all integers are signed.Note: pseudoinstructiosn can have the same name as core instructions but use different operands than the core instructions.
Pseudoinstruction What it accomplishes Actual instructions move x5, x6
x5 = x6
clear x5
x5 = 0
li x5, SMALL
x5 = SMALL
li x6, BIG
x6 =big
assume
BIG[11] = 0li x6, BIG
x6 =big
assume
BIG[11] = 1beq x5, SMALL, L
if (x5 == SMALL) goto L
careful...beq x6, BIG, L
if (x6 == big) goto L
assume
BIG[11] = 0
Pseudoinstruction | What it accomplishes | Actual instructions |
---|---|---|
ble x9, x11, L |
if (x9 <= x11) goto L |
|
bgt x9, x11, L |
if (x9 > x11) goto L |
|
bge x9, x11, L |
if (x9 >= x11) goto L assume you cannot use the bge core instruction for this |
|
addi x6, x13, BIG |
x6 = x13 + big careful... |
|
lw x11, BIG(x13) |
x11 = Mem[x13 + big] |