Toggle past sessions

1: Thu Sep 04 1

• Introduction & Course Overview
  • Read Ch 1 (esp. 1.1-1.3, 1.11)
  • Read A.2, A.3 (decoder/multiplexor) ; 2.4; 3.1-3.2
  • Practice A.11; 2.6
• HW1 review (due Mon Sep 08)
• Note: HWs are always due at class time.

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2: Fri Sep 05 1

• Intro to RISC-V assembly
  • RISC-V green sheet
  • Read 2.1-2.3
  • Practice 2.1-2.4; 2.7-2.8
• RISC-V R Types
  • Arithmetic operations
  • Logical operations
  • Read 2.6
  • Practice 2.17-18,20
• HW2 compiling c into assembly (due Tue Sep 09)

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3: Mon Sep 08 1

• RISC-V I-types, immediates, lw and sw
  • Read 2.10 (Important reading)
• HW3 assembling instructions (due Thu Sep 11)
• Due: * HW1

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4: Tue Sep 09 1

• Practical1 Assembler I (due Mon Sep 15)
• Due: * HW2

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5: Thu Sep 11 2

• RISC-V Branches and Jumps
  • Read 2.7
  • Practice 2.21-22; 2.24; 2.27-28
• HW4 loops (due Mon Sep 15)
• Due: * HW3

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6: Fri Sep 12 2

• Pseudoinstructions
  • Read 2.12 "Assembler" section
• HW5 pseudoinstructions (due Tue Sep 16)

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7: Mon Sep 15 2

• Practical2 Assembler II (due Mon Sep 22)
• Due: * Practical1
• Due: * HW4

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8: Tue Sep 16 2

• Addressing modes
  • Read 2.10 (Important reading)
  • Practice 2.12; 2.22
  • Immediate Translation Handout
• HW6 addressing modes (due Fri Sep 19)
• Due: * HW5

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9: Thu Sep 18 3

• Procedures
  • Read 2.8; (this is an important reading)
  • Practice 2.29-31; 2.33
• HW7 procedure calling (due Mon Sep 22)

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10: Fri Sep 19 3

• Quiz 1
  • See Sample Quiz 1 and (Sample Quiz 1 Solution)
• Due: * HW6

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11: Mon Sep 22 3

• More procedures
  • Read 2.13
• HW8 procedures and loops (due Thu Sep 25)
• Due: * Practical2
• Due: * HW7

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12: Tue Sep 23 3

• Practical3 RISC-V Programming (due Tue Sep 30)

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13: Thu Sep 25 4

• Verilog survival guide 1: Video
• Verilog survival guide 2: Video
• HW9 write verilog code (due Mon Sep 29)
• Due: * HW8

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14: Fri Sep 26 4

• Building Single-Cycle datapath (R-types)
  • Read 4.1-3
  • Practice 4.1-4
• HW10 write relprime (due Fri Oct 03)

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15: Mon Sep 29 4

• Quiz 2
  • See Sample Quiz 2 and (Sample Quiz 2 Solution)
• Due: * HW9

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16: Tue Sep 30 4

• Practical4 Building and Testing Hardware (due Tue Oct 07)
• Due: * Practical3

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17: Thu Oct 02 5

• More Single-Cycle datapath (I-types)
  • Read Single-cycle RTL

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18: Fri Oct 03 5

• Even more Single-Cycle datapath (Branch and Jumps)
• Due: * HW10

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19: Mon Oct 06 5

• Single-Cycle Control
  • Read 4.4
  • Practice 4.4-5
• HW12 single cycle control (due Mon Oct 13)

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20: Tue Oct 07 5

• Practical5 Single-Cycle Processor I (due Thu Oct 16)
• HW11 adding new single cycle instruction (due Tue Oct 14)
• Due: * Practical4

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Break

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21: Mon Oct 13 6

• Other architectures
  • Read 2.16-19
• HW13 various architectures (due Mon Oct 20)
• Due: * HW12

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22: Tue Oct 14 6

• Input/Output
  • Read 2.9
  • Practice 2.38
• Performance
  • Read 1.4-1.9
  • Practice Examples; 1.5–7; 2.39-40
• HW14 performance (due Tue Oct 21)
• Due: * HW11

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23: Thu Oct 16 6

• Practical6 Single-Cycle Processor II (due Thu Oct 23)
• Due: * Practical5

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24: Fri Oct 17 6

• Quiz 3
  • Study HW11
  • See Example Quiz 3 (Example Quiz 3 solution)
• CATME single cycle team eval (due Fri Oct 24)

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25: Mon Oct 20 7

• Pipelined datapath and control
  • Read 4.6-4.7
  • Practice 4.19-20
• CATME pipeline team forming survey (due Thu Oct 23)
• Due: * HW13

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26: Tue Oct 21 7

• More Pipelined datapath and control
• Due: * HW14

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27: Thu Oct 23 7

• Data and control hazards
  • Read 4.8-4.9
  • Practice 4.22; 4.26
• Due: * Practical6
• Due: * CATME pipeline team forming survey

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28: Fri Oct 24 7

• Practical7 Pipelined Processor I (due Thu Oct 30)
• Due: * CATME single cycle team eval

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29: Mon Oct 27 8

• More Pipeline Hazards
  • Read 4.8-4.9
• HW15 pipeline diagrams and efficiency (due Fri Oct 31)

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30: Tue Oct 28 8

• Adding Pipelined Instructions
• HW16 add inst to pipeline (due Fri Nov 07)

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31: Thu Oct 30 8

• Practical8 Pipelined Processor II (due Thu Nov 06)
• Due: * Practical7

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32: Fri Oct 31 8

• Quiz 4
  • Study HW11 and HW12
  • See Example Quiz 4 (Example Quiz 4 solution)
• Due: * HW15

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33: Mon Nov 03 9

• Faster Branching with a Pipelined Processor

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34: Tue Nov 04 9

• Adding more pipelined instructions

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35: Thu Nov 06 9

• Pipelined Performance
• Due: * Practical8

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36: Fri Nov 07 9

• Practical9 Pipelined Processor III (due Thu Nov 13)
• Due: * HW16

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37: Mon Nov 10 10

• Other Architectures II
  • x86 insts
  • x86 encoding
  • ARM insts

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38: Tue Nov 11 10

• Practical 10: Pipeline Design Presentation (The presentation happens during Finals Week.)
• CATME pipeline team eval (due Fri Nov 14)

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39: Thu Nov 13 10

• Wrap up (attendance required)
• Due: * Practical9

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40: Fri Nov 14 10

• Quiz 5
  • Study HW15 and HW16
  • See Example Quiz 5 (Example Quiz 5 solution)
• Due: * CATME pipeline team eval

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