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ece533 | doering | ece labs | ece | rhit |
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Learn about PS/2 port data protocol and timing for keyboards |
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Create your own IP module for a PS/2 keyboard interface |
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Create your own FIFO module |
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Create a top-level design that displays PS/2 scan codes on the seven-segment digit display at a fixed rate |
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Follow good design practice with simulation, i.e., do functional verification for each major module independently, then do verification for the entire system |
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NC-Sim or ModelSim Verilog behavioral simulator |
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Xilinx WebPack ISE 6.3 FPGA implementation tools |
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AT-style keyboard with PS/2 interface connector |
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Digilent D2SB/DIO4 board combination |
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Parallel port cable |
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DC power supply |
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PS/2 Mouse/Keyboard Protocol: http://www.computer-engineering.org/ps2protocol/ |
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The AT-PS/2 Keyboard Interface: http://www.computer-engineering.org/ps2keyboard/ |
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Interfacing the AT Keyboard: http://www.beyondlogic.org/keyboard/keybrd.htm |
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ePanorama PC Hardware Page: http://www.epanorama.net/links/pc/index.html. Look for "Interfaces," then "Keyboard". |
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PLD Oasis > Hardware > Local Guide for Digilent board > Look for "Verilog Modules" section |
NOTE 1: Your design must use of the "datapath / controller" architecture style in at least one module, i.e., use a finite-state machine as a controller of data processing elements.
NOTE 2: Your design must conform to ALL of the Synthesis Design Rules, including the naming conventions at the bottom of the document.
Review the "Verilog Modules" section of Local Guide for Digilent board to learn about two IP modules that I have designed to operate the four-digit display on D2SB/DIO4 (and D2E/DIO1) boards. Use either "DigitDisplay" or "LED7_Display" as your interface to the four-digit display.
Learn about PS/2 data protocol and signal timing in the documents above.
Create a stand-alone PS/2 interface module that can be reused in other designs. The module will accept the PS/2 clock and data signals as input, and produce the keyboard scan code byte as output. The output must be synchronized to the master clock (use the D2SB oscillator) and a "data ready" signal will assert high for one clock cycle when a new scan code is ready. The output must be stable even when a scan code is being read by your module.
Obtain representative waveforms of the PS/2 port from the mixed-signal oscilloscope. Use these waveforms as the basis for a testbench for your PS/2 module. You must create a Verilog "task" that accepts a scan code as an input parameter and produces the correct set of PS/2 data and clock waveforms as output. Look at "taskdemo.v" at PLD Oasis Verilog Examples for a model.
Verify the functionality of your PS/2 interface module with your testbench.
Create a stand-alone FIFO (first-in first-out) memory that will accept scan codes at an arbitrary rate from the PS/2 interface module, and will output the codes at a fixed rate of, say, one or two codes per second. Consider using the block RAM on the Spartan-2E FPGA. The "Registered Dual-Port RAM" may be useful here. [more information forthcoming on this part...]
Create a testbench for the FIFO and verify its functionality. You must do this independently of the PS/2 testbench.
Create a top-level module that instantiates your PS/2 interface, the FIFO, and two seven-segment display drivers.
Create a testbench for your top-level module and verify the functionality of your complete system.
Confirm that your design works properly on the D2SB board.
I/O block diagrams for your PS/2 and FIFO modules, and the top-level module
System block diagram for your top-level module
Hardcopy of mixed-signal oscilloscope PS/2 waveforms
Waveform plots of each of your three functional verifications (include annotations to explain your simulation results)
Hardcopy of all Verilog .v files produced
Memo detailing your design process and results. Describe the operating principles of your PS/2 and FIFO modules.
Demonstration of your design to instructor (obtain initials)
Beginning of lab two week's from today
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