Verilog Examples

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Note 1: Download to get all the files in a single ZIP archive.

Note 2: Some circuits include a ModelSim "do" file (macro file). Add the pair of .v files and the .do file to your ModelSim project, then enter "do" in order to run the testbench simulation.


Description Synthesizable
Simple demonstration of testbench technique demo.v demo_TB.v
Use a "for" loop to efficiently test all possible input combinations of a combinational circuit combi_ckt.v combi_ckt_TB.v
Include text comments in your waveform output to facilitate interpretation   comments.v
Use a "task" to automate the production of waveforms   taskdemo.v

Finite State Machines

Description Synthesizable

FSM using separate 'always' blocks for next-state decoder, output decoder, and state register

fsm_example.v fsm_example_TB.v

Same circuit as above, with testbench decoding the state register to human-readable format

fsm_example2.v fsm_example2_TB.v

Implementation of the example in the Microcoded State Machines tutorial

microcoded.v microcoded_TB.v

Sequential Circuits

Description Synthesizable

Counter with variable step size, and controls for count direction, count enable, and initial value

seq4.v seq4_TB.v

Parameterizable frequency divider

freqdiv.v freqdiv_TB.v

 Advanced Techniques

Description Synthesizable

Use an "`ifdef" compiler directive to set a parameter to one value for simulation and another value for synthesis.

Particularly  useful for clock divider circuits that require a small value for simulation and a large value for synthesis.


Use a "function" to write an algorithmic description of a combinational circuit.

fncdemo.v fncdemo_TB.v

Use the $readmemh system task to fill a memory array with hexadecimal values stored in a file





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Last updated: 03/13/08.