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CSSE232 Practical 1 Worksheet

Read and perform the practical guide posted on the course website. Answer the questions in the practical guide. Numbers in square brackets (e.g. []) indicate the point value of each question. The annotations in parentheses refer to the list of "general practical requirements" from the practical page. The answers to these questions should be as concise as possible. Maintain the spacing provided by this template.

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Full ChatGPT response

“Do all RISC-V instruction formats have a unique opcode?”

No, not all RISC-V instruction formats have a unique opcode. The opcode field in RISC-V is not unique to a specific instruction format. Instead, multiple instruction formats may share the same opcode but are distinguished by other fields (such as funct3, funct7, and others) to differentiate between specific operations.

📚 Understanding the RISC-V Opcode Field

In RISC-V, the opcode is a 7-bit field located at the least significant bits (LSBs) of an instruction. These 7 bits define broad categories of instructions but are shared across multiple formats.

🧱 Common Instruction Formats in RISC-V

Here are the main RISC-V instruction formats:

🔍 Example of Opcode Sharing Consider these two instructions:

  1. ADD x10, x11, x12 (R-type)
  2. ADDI x10, x11, 5 (I-type) Both instructions have the same opcode (0010011), but the format and meaning differ:
Instruction Opcode Format Funct3 Funct7
ADD 0110011 R-Type 000 0000000
ADDI 0010011 I-type 000 N/A

The opcode alone does not determine the exact instruction. Additional fields (funct3, funct7, etc.) are required to distinguish between them.

✅ Summary

  1. Shared Opcodes: Different formats and instructions can share the same opcode.
  2. Differentiation: RISC-V uses other fields like funct3 and funct7 to distinguish between instructions.
  3. Efficiency: This sharing allows for a compact encoding while supporting a wide range of instructions.