1. Final Xilinx Model
For this milestone, your Xilinx model should be completely working and fully tested. Ensure that your project is implemented targeting the Spartan3E family, device xc3s500e, package fg320, speed grade -4 before you collect the data below.
You may modify your register transfer language, datapath, control, or component specifications, but not your assembly language or machine language specifications (unless you obtain instructor approval). Be sure to update the design documentation, and include the changes and their rationale in the final design report.
Evaluate the performance of your design. Collect the following data.
The total number of bytes required to store both Euclid's algorithm and
relPrimeas well as any memory variables or constants.
The total number instructions executed when
relPrimeis called with
0x13B0(the result should be
0x000Busing the algorithm specified in the project specifications).
The total number of cycles required to execute `relPrime under the same conditions as Step 2.
The average cycles per instruction based on the data collected in Steps 2 and 3.
The cycle time for your design (from the Xilinx Synthesis report – look for the Timing summary).
ns = Mhz
The total execution time for
relPrimeunder the same conditions as Step 2.
- The device utilization summary (from the Xilinx Synthesis report).
2. Turning in M6
For this milestone, submit the following:
The updated design document
An complete version of the hardware model.
The updated design process journal.
A summary of the performance data collected above.
Be prepared to demo your processor at your group meeting. Your instructor will have you run your Euclid's program with various input values.
Your (updated) design document, (updated) design process journal, and summary of performance data should be placed in the
Your electronic implementation should be placed in the
Implementation directory of your team's repository.
The names of your design document and design process journal should not change.