Milestone 6

1. Final Quartus Model

For this milestone, your verilog model should be completely working and fully tested. Ensure that your project is implemented targeting the CycloneIV family before you collect the data below.

You may modify your register transfer language, datapath, control, or component specifications, but not your assembly language or machine language specifications (unless you obtain instructor approval). Be sure to update the design documentation, and include the changes and their rationale in the final design report.

Evaluate the performance of your design. Collect the following data.

  1. The total number of bytes required to store both Euclid's algorithm and relPrime as well as any memory variables or constants.

  2. The total number instructions executed when relPrime is called with 0x13B0 (the result should be 0x000B using the algorithm specified in the project specifications).

  3. The total number of cycles required to execute `relPrime under the same conditions as Step 2.

  4. The average cycles per instruction based on the data collected in Steps 2 and 3.

  5. The cycle time for your design:

    1. Set the verilog file that specifies your combined processor and set it as the Top-Level Entity in the right click menu. You need to open your project in Quartus (not ModelSim) and compile it. Once it has finished all the compilation steps you should see this in the Task list:

    2. In the compilation report window you will see a table of contents, select the 'Timing Analyzer' entry, then select the 'Slow 1200mV 85C Model' entry, finally double click the "Fmax Summary" item.

    3. The Fmax report will look something like this, these are the signals Quartus has detected as clocks. Your real clock signal should be here, you can just ignore any other entries. THe Fmax column lists the clock frequency of the design, in the example below 66.22 MHz.

    4. Here is a handy calculator for converting from Hertz to cycle time:
      ns = Mhz

  6. The total execution time for relPrime under the same conditions as Step 2.

  7. The count of logical gates and registers used by your design.

    1. Select the 'Flow Summary' from the table of contents in the compilation report window:

    2. From the Flow Summary you should record the number and percentage of logic elements (i.e. logic gates used on the FPGA), the "Total registers" count, and the "Total memory bits" percentage. An example report is shown here:

2. Turning in M6

For this milestone, submit the following:

Milestone 6

  1. The updated design document

  2. A complete version of the hardware model.

  3. The updated design process journal.

  4. A summary of the performance data collected above.

  5. Be prepared to demo your processor at your group meeting. Your instructor will have you run your Euclid's program with various input values.

Your (updated) design document, (updated) design process journal, and summary of performance data should be placed in the

Your electronic implementation should be placed in the Implementation directory of your team's repository.

The names of your design document and design process journal should not change.