Lab 7 Building a Pipelined Processor


This section is not a list of tasks for you to do. It is a list of skills you will have or things you will know after you complete the lab.

Following completion of this lab you should be able to:


Your Tasks

Follow this sequence of instructions to complete the lab. This lab will all be done in your D-group repository

0 Obtain your C-group git repo

1 Implement R-type datapath (no control yet)

  1. Trace on the provided DP diagram

  2. Design your pipeline stage registers' contents

    • build each, call them IF_ID_Reg, etc. so the instances can be IF_ID or similar.
    • For each "thing" in the register, make the output named that thing, and an input should have the same name with an _in suffix. For example:
      input wire [31:0] inst_in,
      output reg [31:0] inst,
    • Be sure to include the clock as an input.
    • In the body of the module, create an always block to copy the inputs to their corresponding outputs.
  3. Create Processor.v that has instances of all your pipeline stage registers

  4. Between the registers, instantiate the components you need

    • Register File
    • PC
    • ALU
    • No data memory yet (use DP_Memory.v from lab, but only connect the "A" ports.)
  5. Connect the components to your pipeline stage registers

  6. The Memory cycle will just pass data through from EX_MEM to MEM_WB.

  7. Your WB cycle will refer to the register file in your ID cycle.

2 Add control to your datapath

  1. Use your single cycle control!
  2. Put it into ID
  3. Write the EX/Mem/WB outputs into your ID_EX pipeline stage register
  4. Update all your stage registers to have control blocks.

3 First Test in modelsim


  1. Edit our basic R-type test to use your processor (see comments in test).
  2. New modelsim project
    • Add all the .v files
    • compile
    • run the basic test
  3. Build a waveform to show all your stages.
    • add a divider between each stage
  4. HINT: do in the console will add some new "Radix" values that will display opcodes and functs as useful words.
  5. Save your waveform.
  6. Run the tests
  7. Fix any errors.

4 Add support for the remaining R-types

  1. Do it
  2. Test R-types using tb_Pipe.v
    • Edit the pipeline_test_tools.vh file
    • Tour of test bench file?

5 Add I-types (no data memory yet)

  1. Trace on dp diagram
  2. Add any new traced wires to verilog datapath
  3. Add control (or connect it)
    • You'll need an ALUSrc mux
  4. Write tests (here's some assembly. Assemble this with your assembler, then add new task to tb_Pipe.v to use it.
  5. Run tests
  6. On worksheet, explain why this set of instructions is sufficient to test I-types, or how you changed it to be better.

6 If you have time...

Work ahead (go start Lab 8)

Turn It In

Grading Rubric

General Requirements for all Labs:

  1. fits the need
  2. discuss performance
  3. tests for correctness
  4. iteration and documentation

Fill out the Lab Worksheet

In the worksheet, explain how you satisfy each of these items. Some guidelines:

Lab 7 Rubric items Possible Points
Lab Worksheet 25
R-Type and tests 30
I-Type and tests 30
Custom Tests 10
Extra points 5
Total out of 100

For extra points, you could:

  1. Submit your completed Lab Worksheet to gradescope.

  2. Lab code will be submitted to your D git repository as new files and committed modifications to the repo we provided you. You must include your name and your teammates' names in a comment at the top of all files you submit.