CSSE232 : Computer Architecture I

Name: Date:

HW9 solution

Consider the verilog code for the module THING described below.
```
module THING(
    input wire [3:0] din,
    output wire [3:0] dout
)

always @(din) begin
    dout = din + 1;
end
endmodule
```
a. (4 points) This module will not compile, it gives an error that says something like 'Illegal reference to net "dout"'. Explain why this error happens and how to fix it.

dout is declared as a wire, because we are driving the signal inside an always block it must be a reg type instead. (Or we need to use an assign statement instead of an always block.)

b. (4 points) This module has very simple behavior, we could use an assign statement to implement the same behavior as the always block. Write the equivalent assign statement.

assign dout = din + 1;

c. (4 points) If we used the assign statement you built in question b and made no other changes to the starting code would the compilation error from question a still happen? Explain.

No, the error is gone because assign can drive wires. As long as each wire is associated with only a single assign statement.

(7 points) a. Fill in the definition of the module below. This module stores a number which starts out at 0, and outputs it constantly. At the negative edge of the clock it increments the stored number.
```
 module Incrementor(
     input wire CLK,
     output reg [31:0] dout
 );

 reg [31:0] value = 0;

 always @(negedge CLK) begin
     value = value + 1;
     dout = value;
 end
 endmodule
```
or, alternatively:
```
 initial begin
     dout = 0;//make sure we set the initial value
 end

 always @(negedge CLK) begin
     dout = dout + 1;
 end
 endmodule
```
b . (3 points) Explain why we can't simply use an assign statement to drive the output in a clocked module, like this one.

Because this logic is not continuous, and we only want to change the output at a predictable interval (on the negative clock edge) we have to use an always block to "watch" the clock and only execute at certain times. We do not want to update the output as soon as the inputs change.