Name: Date:


  1. (6 points) Convert the following C code to RISC-V assembly instructions. Use the minimum number of instructions necessary. Assume that variables f, g and h are 32- bit integers stored in registers x5, x6 and x7 respectively and that the base address of arrays A and B are in registers x8 and x9 respectively. A and B are arrays of 4-byte integers (this is important). If you need to store temporary values, use one of the other registers.
    a. f = 1; A[f] = 0;

    b. B[1] = A[f-5];

  2. (4 points) Show the hexadecimal representation of the following RISC-V instructions. Show your work.
    a. addi x7, x7, 4

    b. lw x9, 8(x5)

  3. (5 points) Consider changing the RISC-V instruction set to support 64 registers instead of 32. Assuming changes are made only to the register fields, draw the new R-type instruction format. Be sure to label each field and include its size.

  4. (5 points) How many possible R-type instructions does RISC-V support if every possible combination of opcode, funct7, and funct3 are valid instructions? (You can ignore other instruction types for this question.)