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## HW4 solution

1. (6 points) Convert the following C code to MIPS assembly instructions. Use the minimum number of instructions necessary. Assume that variables f, g and h are 32- bit integers stored in registers $t0, $t1 and $t2 respectively and that the base address of arrays A and B are in registers $s3 and $s4 respectively. A and B are arrays of 4-byte integers (this is important). If you need to store temporary values, use one of the other t registers. a. f = 1; A[f] = 0; addi$t0, $0, 1 sll$t7, $t0, 2 add$t7, $s3,$t7
sw   $0, 0($t7)

b. B[1] = A[f-5];

sll  $t7,$t0, 2    #make offset for A[f]
add  $t7,$s3, $t7 #add base to offset for A[f] lw$t7, -20($t7) #get value for A[f-5] sw$t7, 4($s4) 2. (4 points) Show the hexadecimal representation of the following MIPS instructions. Show your work. a. addi$s0, $s0, 4 Needs to show the decomposition into op | rs | rt | rd | sh | fn for full credit. 0x22100004 b. lw$s1, 8(\$t0)

Needs to show the decomposition into op | rs | rt | imm for full credit.
0x8d110008

3. (5 points) Consider changing the MIPS instruction set to support 64 registers instead of 32. Assuming changes are made only to the register fields, draw the new R-type instruction format. Be sure to label each field and include its size.

op rs rt rd shamt func
6 6 6 6 5 6

Total size of 35 bits

4. (5 points) How many total instructions does MIPS support if opcode 000000 is the only opcode used for R-types? Remember that R-types also use a function code.

If opcode 000000 is reserved for R-types, that leaves the rest of the op-codes for instructions. So there are $$2^{32} - 1$$ instructions that can be defined by the op-code. Since the R-types use the function code to indicate the instruction, there are $$2^{32}$$ possible R-types.

$$|inst| = 2^{6}-1 + 2^{6} = 127$$