Name: Date:


  1. (10 points) Draw the pipeline diagram for the following code running on a pipelined RISC-V processor. Identify all of the data dependencies (draw forwards and stalls).

    add x3, x4, x2
    sub x5, x3, x1
    lw  x6, 200(x3)
    add x7, x3, x6

    Which of the above dependencies are data hazards that will be resolved via forwarding? Which dependencies are data hazards that will cause a stall?

  1. (10 points) Consider the following code to be run on a pipelined RISC-V processor:

    lw   x4, 4(x5)
    lw   x3, 0(x5)
    add  x7, x7, x3
    addi x5, x5, 4
    sw   x6, 0(x5)
    add  x8, x8, x4
    beq  x7, x8, loop

    a. Reorder the instructions to maximize performance. Performance may already by maximized.

    b. Reorder the instructions to minimize performance. Performance may already be minimized.

  2. (10 points) We wish to add a variant of the lw (load word) instruction, which increments the index register after loading the word from memory. This instruction (l_inc) corresponds to the following two instructions:

    lw   rd, L(rs1)
    addi rs1, rs1, 4

    Describe the changes you would need to make to the datapath. You may need to make major changes to the pipeline! Do your changes affect other instructions?