Name: Box: Date:
(10 points) Draw the pipeline diagram for the following code running on a pipelined MIPS processor. Identify all of the data dependencies (draw forwards and stalls).
add $3, $4, $2 sub $5, $3, $1 lw $6, 200($3) add $7, $3, $6
Which of the above dependencies are data hazards that will be resolved via forwarding? Which dependencies are data hazards that will cause a stall?
(5 points) Modify the following code to make use of the delayed branch slot on a pipelined MIPS processor.
loop: lw $2, 100($3) sub $4, $4, $5 beq $3, $4, loop
(10 points) Consider the following code to be run on a pipelined MIPS processor:
lw $4, 4($5) lw $3, 0($5) add $7, $7, $3 addi $5, $5, 4 sw $6, 0($5) add $8, $8, $4 beq $7, $8, loop nop #this delay slot is currently empty
a. Reorder the instructions to maximize performance. Performance may already by maximized.
b. Reorder the instructions to minimize performance. Performance may already be minimized.
(10 points) We wish to add a variant of the lw (load word) instruction, which increments the index register after loading the word from memory. This instruction (l_inc) corresponds to the following two instructions:
lw $rt, L($rs) addi $rs, $rs, 4
Describe the changes you would need to make to the datapath. You may need to make major changes to the pipeline! Do your changes effect other instructions?