Name: Date:

HW14

You are the lead designer of a processor and wish to evaluate design options and pick the most efficient. For all problems show your work and include units in your calculations for full credit.

  1. (3 points) Base deisgn You first analyze the current design, Mbase, which has a clock rate of 2.5 GHz. (Note that Hz = cycles/second, track your units carefully.) Testing with a benchmark program yields the measurements below. What is the execution time of this porgram.

    Instruction Class CPI Count
    R 1 40
    I 1 25
    Mem 1 25
    SB/J 1 10
  2. Your team is going to add the l_inc instruction (from HW11) to your processor.

    a. (2 points) What effect is this likely to have on the cycle time? Justify your answer by explaining how the critical path changes with the addition of this instruction.

    b. (3 points) Estimate the new cycle time. Assume that each piece of hardware takes these amounts of time to execute: Memory - 2ns, ALU - 2ns, registers - 1ns, others - 0ns.

  3. Your team is going to add the add4_mem instruction, which does the following: rd = Mem[rs1+imm] + 4

    a. (2 points) What effect is this likely to have on the cycle time? Justify your answer by explaining how the critical path changes with the addition of this instruction.

    b. (3 points) Estimate the new cycle time. Assume that each piece of hardware takes these amounts of time to execute: Memory - 2ns, ALU - 2ns, registers - 1ns, others - 0ns.

  1. Your team creates two new compilers, each one uses one of the new instructions described above. C1 incorporates the lw_inc instruction, while C2 incorporates the add4_mem instruction.

    a. (6 points) Estimate the execution time for the compiled program on each of the modified processor designs you discuss above.

    Instruction Class CPI C1 Count C2 Count
    R 1 30 35
    I 1 25 20
    Mem 1 25 20
    SB/J 1 10 10

    b. (3 points) You realize that your team can only implement one of these two new instructions. Which one should your team implement? Or shoudl they stick with the base RISC-V design? Justify your answer.