Name: Box: Date:
HW13 solution
(20 points) We wish to add a variant of the lw (load word) instruction, which increments the index register after loading the word from memory. This instruction (l_inc) corresponds to the following two instructions:
lw $rt, L($rs)
addi $rs, $rs, 4Add any necessary datapaths and control signals to the single-cycle datapath of Figure 4.17 on page 265 and show the necessary additions to Figure 4.18 on page 266.
- Write the RTL for this new instruction. It may be helpful to review the RTL on the course website.
The RTL for this instruction might look something like:
PC = PC+4
inst = Mem[PC]
a = Reg[ inst[15-11] ]
i = a + 4
m = a + SE( inst[15-0] )
r = Mem[ m ]
Reg[ inst[25-21] ] = r
Reg[ inst[20-16] ] = i- Adjust the datapth figure (attached) to execute your RTL.
The best solution to this problem is to add a new write capabilities to the register file. The new register file will have a new write address port (5 bits) and a new write data port (32 bits).
This necessitates a new RegWrite signal, so we will have RegWrite1 for the normal data and
RegWrite2 for the new ports.
This control signal should only be enabled for the new l_inc instruction.
Additionally, a new adder must be added to support the increment by 4 operation.
This adder takes as input the output of the register file's first read port and a constant 4.
The output is routed to the new write data port on the register file.
Finally, the wires for rs (inst[25-21]) need to routed to the register file's new write address port.
- Provide an updated set of control signals for the new instruction.
| Instruction name | RegDst | ALUSrc | ALUOp | MemtoReg | RegWrite | MemRead | MemWrite | Branch | RegWrite2 |
|---|---|---|---|---|---|---|---|---|---|
| l_inc | 0 | 1 | 00 | 1 | 1 | 1 | 0 | 0 | 1 |
Modify this figure for your instruction.
