Milestone 2

1 Register Transfer Language Specification

Now that your assembly language and machine language specifications are complete, you should describe how you plan to implement your instruction set at the register transfer level (RTL).

Your first step in this process is to break each instruction into small steps. Each step should be of roughly equal size (i.e. they should take about the same amount of time to complete) and move data from one register to another. Complete the process by grouping steps that can be completed in parallel in a single clock cycle. Be sure to look for common steps across all of your instructions. Exploiting these can simplify your implementation.

Next, list and describe the components required to implement your RTL (e.g. "S/E is a combinational logic unit that sign-extends an 8-bit input to produce a 16-bit output"). Make sure that resources are not over used. Normally, each component may only be used once each clock cycle. For this milestone, you are only interested in the components that are clearly needed by the RTL.

Note: Xilinx block memory does not output values from memory until the rising edge of the clock (i.e. it is synchronous). This is different from the assumption that the book makes about memory!

Be aware that your RTL specification directly impacts performance (execution time) of and resources (the number of gates) required to implement your design. Specifically the time required to complete the longest step determines the cycle time (clock frequency) and the number of groups required to complete an instruction determines the CPI. If you plan on doing single-cycle, you don't need registers between the stages. Instead, just indicate that wires are holding information between the stages. That is, instead of having your instruction in \texttt{IR}, you might have your instruction on the \texttt{inst} wires.

You may modify your assembly language and machine language specifications for this milestone. In fact, time spent getting the instruction set architecture correct for this milestone will save you lots of time later. Please note any changes and why they were made in your design process journal.

Do not build any datapath or control for this milestone. You need to verify your RTL is robust before continuing.

You will model, test, and debug your complete processor using the Xilinx ISE design suite. It is highly recommended that you begin implementing and testing individual components in a bottom-up manner now.

2 Turning It In

For this milestone, you will submit the following:

  1. An updated design document, that includes the following:
    • An RTL description of each instruction or set of related instructions. You should include a summary chart similar to the ones discussed in class.

    • A list of components needed to implement your register transfer language (these will eventually make up your datapath).

      • A list of input signals, output signals, and control signals for each component, including the number of bits in each signal.

      • An unambiguous English description of how each component's output will change according to its input and control signals.

    • Descriptions of the tests necessary to verify the correct implementation of your RTL description. Please be as specific as possible, and avoid generalizations, for example, instead of saying ``test basic math operations of the ALU'', list out addition, subtraction, etc. and give at least one thoughtful example of each type of test, be sure to consider edge and corner cases.

    • A note of changes made to the Assembly language and Machine language specifications.

  2. An updated design process journal, including your thought processes and rationale behind your decisions.

Your design documents should be placed in the Design directory of your team's repository. I will refer to this rubric when grading.

Your implementation should be placed in the Implementation directory of your team's repository.

The names of your design documents and design process journal should not change.