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CSSE 232 Computer Architecture I
	Resources
Home Syllabus Policies Communication Homework Project Resources Handouts

	Handouts
R-00	Project Resources
R-01	Introduction to MIPS and SPIM  Solution
R-02	Conditional Statements Solution to p04-1.asm Solution to p04-2.asm
R-03	Procedures p05-2-soln-1.asm
R-04	Exceptions p06-1.asm  Cause and Status Registers
R-05	Xilinx Installation
R-06	Exam 1 Fall 2003-2004    Solution
R-07	Exam 1 Winter 2003-2004 Solution
R-08	Datapath (lui and jal)
R-09	Control (Single cycle, Multi-cycle, FSM design)
R-10	Xilinx Introduction I (Project Navigator, Schematic Editor, HDL Bencher, ModelSim simulator and Core Generator)
R-11	Xilinx Introduction II (StateCad)
R-12	Xilinx Introduction III (Hierarchical design flow)
R-13	Xilinx Introduction IV (Including Verilog files) Resources for Verilog (Courtesy Dr. Doering)
R-14	ALU construction slides
R-15	Exam 2 Fall 2003-2004 Solutions to Problems 3 and 4. Solution to Problem 1(a) Problem 1(b)  Solution to Problem 2
R-16	Performance (slides from class)
R-17	Sample Verilog files(Instructions)  Files(compressed)
R-18	Xilinx Introduction V(Size and timing constraints) Easy16.rar  VLogALU.rar
R-19	Stacks and Recursion

Last modified: Thursday February 12, 2004