IA-64 is Intel's 64-bit instruction set archicture. IA-64 was co-developed with HP starting in 1994. Recently, Intel and HP have made public disclosures regarding the instruction set architecture. Since the design philosophy behind IA-64 is based on separating dynamic (runtime) and static (compile time) functionality, this tutorial covers an overview of the IA-64 architecture and how to use its features to optimize code and compiler technology for implementing such transformations. Since dynamic compilation/dynamic translators are becoming a mainstream technology, we also provide a brief introduction to Java and dynamic compilation on IA-64.
The optimization section of the tutorial will describe specific optimizations that take advantage of the IA-64 features, when to apply such transformations, and general considerations that should be taken into account when and when not to apply the transformations.
The compiler section of the tutorial will describe compiler technology on the IA-64 architecture, which includes special optimizations particularly designed for the architectural features. The section will discuss the integration of these special optimizations with conventional compiler components in IA-64 compiler design. The tutorial will briefly describe dynamic compilation technology such as JVM/JIT on IA-64 as well.
The goal of data compression is to provide the most efficient way to represent information in terms of storage and transmission time. This goal is accomplished by developing techniques that exploit different redundancies that may be present in data. Information can be in a variety of forms, such as text, image, video, and voice, each having its own specific type of redundancies. In the first part of the tutorial, we will look at a variety of techniques that exploit redundancy present in data to provide efficient representations of information. Standards like CCITT-G3, -G4, JBIG, JPEG, and MPEG will be addressed in detail.
In the second half of this tutorial we will discuss the latest parallel techniques used in enhancing the performance of microprocessors to handle multimedia tasks. In particular, we will talk about VLIW and its impact on the multimedia hardware. Moreover, there will be an extensive presentation on the notion of subword parallelism and reincarnation of limited SIMD in the realm of modern microprocessors that are already performing to their limits by using superscalar technology. We will talk about the underlying theory and in particular instruction set design for these machines. The data transfer techniques is another topic that will be covered where its impact on the performance is considered critical. Finally, we will cover case studies of existing parallel microprocessor architectures where general purpose architectures are compared with multimedia coprocessors. In conclusion, we will present an outlook for what we should expect in the next five years and its impact on the multimedia and internet.
Back to PACT'99 homepage