;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.36 *
;* Date/Time created: Wed Mar 17 10:09:16 2004 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C670x *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : No Debug Info *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.global _buffer
_buffer: .usect "SDRAM",24576,4
.sect ".cinit:c"
.align 8
.field (CIR - $) - 8, 32
.field _buffer_ready+0,32
.field 0,16 ; _buffer_ready @ 0
.sect ".text"
.global _buffer_ready
_buffer_ready: .usect ".bss:c",2,2
.sect ".cinit:c"
.align 2
.field 0,16 ; _over_run @ 0
.sect ".text"
.global _over_run
_over_run: .usect ".bss:c",2,2
.sect ".cinit:c"
.align 2
.field 0,16 ; _ready_index @ 0
.sect ".text"
.global _ready_index
_ready_index: .usect ".bss:c",2,2
.global _sineObjL
.bss _sineObjL,56,4
.global _sineObjR
.bss _sineObjR,56,4
.global _rDelayBuff
.bss _rDelayBuff,4096,4
.bss _Left$1,8192,4
.bss _Right$2,8192,4
.sect ".cinit:c"
.align 4
.word 03f800000h ; _lVol$3 @ 0
.sect ".text"
_lVol$3: .usect ".bss:c",4,4
.bss _rVol$4,4,4
; c:\ti\c6x\c6000\cgtools\bin\opt6x.exe -v6700 -q -O3 C:\DOCUME~1\morrow\LOCALS~1\Temp\TI1664_2 C:\DOCUME~1\morrow\LOCALS~1\Temp\TI1664_5 -w C:/My Work/Yoder/lab6/Frame_EDMA\\Release
.sect ".text"
.global _ZeroBuffers
;******************************************************************************
;* FUNCTION NAME: _ZeroBuffers *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
;* B6,B7,B8,B9,B13,SP *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
;* B6,B7,B8,B9,B13,DP,SP *
;* Local Frame Size : 0 Args + 0 Auto + 8 Save = 8 byte *
;******************************************************************************
_ZeroBuffers:
;** --------------------------------------------------------------------------*
MVKL .S1 _buffer-8,A0 ; |48|
MVKH .S1 _buffer-8,A0 ; |48|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 50
;* Loop opening brace source line : 51
;* Loop closing brace source line : 51
;* Loop Unroll Multiple : 2x
;* Known Minimum Trip Count : 3072
;* Known Maximum Trip Count : 3072
;* Known Max Trip Count Factor : 3072
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1* 0
;* .D units 1* 1*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 1*
;* Long read paths 1* 1*
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1* 0
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 1 Schedule found with 7 iterations in parallel
;* Done
;*
;* Epilog not entirely removed
;* Collapsed epilog stages : 3
;* Collapsed prolog stages : 0
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 4 (after unrolling)
;*----------------------------------------------------------------------------*
L1: ; PIPED LOOP PROLOG
B .S1 L2 ; |51| (P) <0,1>
B .S1 L2 ; |51| (P) <1,1>
MVK .S2 0xc00,B4 ; |50|
|| B .S1 L2 ; |51| (P) <2,1>
ZERO .S2 B5
|| STW .D2T1 A10,*SP--(8) ; |46|
|| SUB .L2 B4,9,B0
|| B .S1 L2 ; |51| (P) <3,1>
ZERO .D1 A3
|| STW .D2T2 B13,*+SP(4) ; |46|
|| MV .L2 B3,B13 ; |46|
|| ADD .S2X 4,A0,B4
|| B .S1 L2 ; |51| (P) <4,1>
;** --------------------------------------------------------------------------*
L2: ; PIPED LOOP KERNEL
STW .D1T1 A3,*++A0(8) ; |51| <0,6>
|| STW .D2T2 B5,*++B4(8) ; |51| <0,6>
|| [ B0] B .S1 L2 ; |51| <5,1>
|| [ B0] SUB .S2 B0,1,B0 ; |51| <6,0>
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 53
;* Loop opening brace source line : 53
;* Loop closing brace source line : 55
;* Loop Unroll Multiple : 2x
;* Known Minimum Trip Count : 512
;* Known Maximum Trip Count : 512
;* Known Max Trip Count Factor : 512
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1* 0
;* .D units 1* 1*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 1*
;* Long read paths 1* 1*
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1* 0
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 1 Schedule found with 7 iterations in parallel
;* Done
;*
;* Epilog not entirely removed
;* Collapsed epilog stages : 1
;* Collapsed prolog stages : 0
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 6 (after unrolling)
;*----------------------------------------------------------------------------*
L3: ; PIPED LOOP EPILOG AND PROLOG
MVK .S2 (_rDelayBuff-8-$bss),B6
|| STW .D1T1 A3,*++A0(8) ; |51| (E) <4,6>
|| STW .D2T2 B5,*++B4(8) ; |51| (E) <4,6>
|| B .S1 L4 ; |55| (P) <0,1>
MVK .S2 0x200,B6 ; |53|
|| ADD .L2 DP,B6,B7
|| STW .D2T2 B5,*++B4(8) ; |51| (E) <5,6>
|| STW .D1T1 A3,*++A0(8) ; |51| (E) <5,6>
|| B .S1 L4 ; |55| (P) <1,1>
SUB .S2 B6,11,B0
|| ZERO .L2 B5
|| ZERO .L1 A3
|| STW .D1T1 A3,*++A0(8) ; |51| (E) <6,6>
|| STW .D2T2 B5,*++B4(8) ; |51| (E) <6,6>
|| B .S1 L4 ; |55| (P) <2,1>
ADD .D2 4,B7,B4
|| MV .L1X B7,A0
|| B .S1 L4 ; |55| (P) <3,1>
B .S1 L4 ; |55| (P) <4,1>
;** --------------------------------------------------------------------------*
L4: ; PIPED LOOP KERNEL
STW .D1T1 A3,*++A0(8) ; |54| <0,6>
|| STW .D2T2 B5,*++B4(8) ; |54| <0,6>
|| [ B0] B .S1 L4 ; |55| <5,1>
|| [ B0] SUB .S2 B0,1,B0 ; |55| <6,0>
;** --------------------------------------------------------------------------*
L5: ; PIPED LOOP EPILOG
MVKL .S2 RL0,B3 ; |57|
|| MVKL .S1 0x472c4400,A10 ; |57|
|| STW .D2T2 B5,*++B4(8) ; |54| (E) <2,6>
|| STW .D1T1 A3,*++A0(8) ; |54| (E) <2,6>
MVKH .S1 0x472c4400,A10 ; |57|
|| CALL .S2 _SINE_init ; |57|
|| STW .D2T2 B5,*++B4(8) ; |54| (E) <3,6>
|| STW .D1T1 A3,*++A0(8) ; |54| (E) <3,6>
MVKH .S2 RL0,B3 ; |57|
|| MV .S1 A10,A6 ; |57|
|| STW .D1T1 A3,*++A0(8) ; |54| (E) <4,6>
|| STW .D2T2 B5,*++B4(8) ; |54| (E) <4,6>
STW .D2T2 B5,*++B4(8) ; |54| (E) <5,6>
|| STW .D1T1 A3,*++A0(8) ; |54| (E) <5,6>
STW .D1T1 A3,*++A0(8) ; |54| (E) <6,6>
|| STW .D2T2 B5,*++B4(8) ; |54| (E) <6,6>
ZERO .D2 B4 ; |57|
|| MVK .S1 (_sineObjL-$bss),A0 ; |57|
ADD .S1X DP,A0,A4 ; |57|
|| MVKH .S2 0x43dc0000,B4 ; |57|
RL0: ; CALL OCCURS ; |57|
CALL .S2 _SINE_init ; |58|
MV .D1 A10,A6 ; |57|
|| ZERO .D2 B4 ; |58|
|| MVK .S1 (_sineObjR-$bss),A0 ; |58|
|| MVKL .S2 RL1,B3 ; |58|
ADD .S1X DP,A0,A4 ; |58|
|| MVKH .S2 0x445c0000,B4 ; |58|
MVKH .S2 RL1,B3 ; |58|
NOP 2
RL1: ; CALL OCCURS ; |58|
NOP 1
LDW .D2T2 *+SP(4),B13 ; |59|
|| MV .S2 B13,B3 ; |59|
RET .S2 B3 ; |59|
|| LDW .D2T1 *++SP(8),A10 ; |59|
NOP 5
; BRANCH OCCURS ; |59|
.sect ".text"
.global _ProcessBuffer
;******************************************************************************
;* FUNCTION NAME: _ProcessBuffer *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2, *
;* B3,B4,B5,B6,B7,B8,B9,B10,B11,SP *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2, *
;* B3,B4,B5,B6,B7,B8,B9,B10,B11,DP,SP *
;* Local Frame Size : 0 Args + 0 Auto + 20 Save = 20 byte *
;******************************************************************************
_ProcessBuffer:
;** --------------------------------------------------------------------------*
LDH .D2T2 *+DP(_ready_index),B4 ; |76|
STW .D2T1 A12,*SP--(24) ; |75|
NOP 2
MVKL .S1 _buffer,A0 ; |76|
|| MVC .S2 CSR,B7
|| STW .D2T2 B11,*+SP(20) ; |75|
MVKH .S1 _buffer,A0 ; |76|
|| AND .L2 -2,B7,B6
|| STW .D2T2 B10,*+SP(16) ; |75|
|| SHL .S2 B4,13,B4 ; |76|
MVC .S2 B6,CSR ; interrupts off
|| STW .D2T1 A11,*+SP(12) ; |75|
|| MVK .S1 0x800,A0 ; |92|
|| ADD .L1X A0,B4,A3 ; |76|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 92
;* Loop opening brace source line : 92
;* Loop closing brace source line : 95
;* Known Minimum Trip Count : 2048
;* Known Maximum Trip Count : 2048
;* Known Max Trip Count Factor : 2048
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 2*
;* .S units 1 0
;* .D units 2* 2*
;* .M units 0 0
;* .X cross paths 0 2*
;* .T address paths 2* 2*
;* Long read paths 0 2*
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 0 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 2*
;*
;* Searching for software pipeline schedule at ...
;* ii = 2 Schedule found with 6 iterations in parallel
;* Done
;*
;* Epilog not removed
;* Collapsed epilog stages : 0
;*
;* Prolog not entirely removed
;* Collapsed prolog stages : 3
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh12
;*
;* Minimum safe trip count : 5
;*----------------------------------------------------------------------------*
L6: ; PIPED LOOP PROLOG
STW .D2T1 A10,*+SP(8) ; |75|
|| SUB .D1 A3,4,A3
|| B .S1 L7 ; |95| (P) <0,5>
MVK .S2 (_Left$1-$bss),B5 ; |78|
|| SUB .S1 A0,5,A1
|| LDH .D1T1 *++A3(4),A0 ; |93| (P) <0,0>
MVK .S2 (_Right$2-$bss),B4 ; |78|
|| LDH .D1T1 *+A3(2),A0 ; |94| (P) <0,1>
|| B .S1 L7 ; |95| (P) <1,5>
MVK .S1 0x3,A2 ; init prolog collapse predicate
|| ADD .D2 DP,B4,B5 ; |78|
|| ADD .S2 DP,B5,B4 ; |78|
|| MV .L2 B3,B11 ; |75|
|| LDH .D1T1 *++A3(4),A0 ; |93| (P) <1,0>
;** --------------------------------------------------------------------------*
L7: ; PIPED LOOP KERNEL
[!A2] STW .D2T2 B6,*B5++ ; |93| <0,9>
|| INTSP .L2X A0,B6 ; |93| <2,5>
|| [ A1] B .S1 L7 ; |95| <2,5>
|| LDH .D1T1 *+A3(2),A0 ; |94| <4,1>
[ A2] SUB .S1 A2,1,A2 ; <0,10>
|| [!A2] STW .D2T2 B6,*B4++ ; |94| <0,10>
|| INTSP .L2X A0,B6 ; |94| <2,6>
|| [ A1] SUB .L1 A1,1,A1 ; |95| <3,4>
|| LDH .D1T1 *++A3(4),A0 ; |93| <5,0>
;** --------------------------------------------------------------------------*
L8: ; PIPED LOOP EPILOG
MVK .S1 (_sineObjL-$bss),A3
|| INTSP .L2X A0,B6 ; |93| (E) <3,5>
|| LDH .D1T1 *+A3(2),A0 ; |94| (E) <5,1>
|| STW .D2T2 B6,*B5++ ; |93| (E) <1,9>
MVK .S1 0x800,A10 ; |147|
|| ADD .L1X DP,A3,A11
|| STW .D2T2 B6,*B4++ ; |94| (E) <1,10>
|| INTSP .L2X A0,B6 ; |94| (E) <3,6>
INTSP .L2X A0,B6 ; |93| (E) <4,5>
|| STW .D2T2 B6,*B5++ ; |93| (E) <2,9>
STW .D2T2 B6,*B4++ ; |94| (E) <2,10>
|| INTSP .L2X A0,B6 ; |94| (E) <4,6>
INTSP .L2X A0,B6 ; |93| (E) <5,5>
|| STW .D2T2 B6,*B5++ ; |93| (E) <3,9>
STW .D2T2 B6,*B4++ ; |94| (E) <3,10>
|| INTSP .L2X A0,B6 ; |94| (E) <5,6>
STW .D2T2 B6,*B5++ ; |93| (E) <4,9>
STW .D2T2 B6,*B4++ ; |94| (E) <4,10>
MVC .S2 B7,CSR ; interrupts on
|| STW .D2T2 B6,*B5++ ; |93| (E) <5,9>
;** --------------------------------------------------------------------------*
STW .D2T2 B6,*B4++ ; |94| (E) <5,10>
MVK .S2 (_Left$1-$bss),B4 ; |78|
ADD .D2 DP,B4,B10 ; |78|
MV .S1X B10,A12 ; |78|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;* Disqualified loop: Loop contains a call
;*----------------------------------------------------------------------------*
L9:
CALL .S1 _sineGen ; |148|
MVKL .S2 RL2,B3 ; |148|
MVKH .S2 RL2,B3 ; |148|
MV .D1 A11,A4 ; |148|
NOP 2
RL2: ; CALL OCCURS ; |148|
LDW .D2T2 *+DP(_lVol$3),B4 ; |148|
INTSP .L1 A4,A0 ; |148|
LDW .D2T2 *B10,B5 ; |148|
SUB .D1 A10,1,A1 ; |152|
SUB .D1 A10,1,A10 ; |152|
MPYSP .M2X B4,A0,B4 ; |148|
NOP 2
[ A1] B .S1 L9 ; |152|
ADDSP .L2 B4,B5,B4 ; |148|
NOP 3
STW .D2T2 B4,*B10++ ; |148|
; BRANCH OCCURS ; |152|
;** --------------------------------------------------------------------------*
LDH .D2T2 *+DP(_ready_index),B4 ; |164|
NOP 1
MVK .S1 (_Right$2-$bss),A0 ; |78|
|| MVC .S2 CSR,B9
MVKL .S1 _buffer,A3 ; |76|
|| AND .S2 -2,B9,B6
MVKH .S1 _buffer,A3 ; |76|
|| MVC .S2 B6,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 174
;* Loop opening brace source line : 174
;* Loop closing brace source line : 177
;* Known Minimum Trip Count : 2048
;* Known Maximum Trip Count : 2048
;* Known Max Trip Count Factor : 2048
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 1 1
;* .S units 2* 1
;* .D units 2* 2*
;* .M units 1 1
;* .X cross paths 0 1
;* .T address paths 2* 2*
;* Long read paths 1 1
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 2* 1
;* Bound(.L .S .D .LS .LSD) 2* 2*
;*
;* Searching for software pipeline schedule at ...
;* ii = 2 Schedule found with 9 iterations in parallel
;* Done
;*
;* Epilog not removed
;* Collapsed epilog stages : 0
;*
;* Prolog not entirely removed
;* Collapsed prolog stages : 6
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh20
;*
;* Minimum safe trip count : 8
;*----------------------------------------------------------------------------*
L10: ; PIPED LOOP PROLOG
ZERO .D2 B5
|| MV .L2X A12,B4 ; |165|
|| B .S1 L11 ; |177| (P) <0,11>
|| SHL .S2 B4,13,B6 ; |164|
MVKH .S2 0x47800000,B5
|| LDW .D2T2 *B4++,B6 ; |176| (P) <0,0>
|| ADD .L2X A3,B6,B6 ; |164|
|| ADD .S1X DP,A0,A3 ; |78|
MVK .S2 0x800,B7 ; |174|
|| MV .L1X B5,A0
|| SUB .D2 B6,4,B5
|| LDW .D1T1 *A3++,A8 ; |175| (P) <0,1>
|| B .S1 L11 ; |177| (P) <1,11>
MVK .S1 0x800,A1 ; init prolog collapse predicate
|| SUB .S2 B7,5,B0
|| SUB .L1X B6,4,A5
|| ADD .L2 2,B5,B5
|| LDW .D2T2 *B4++,B6 ; |176| (P) <1,0>
;** --------------------------------------------------------------------------*
L11: ; PIPED LOOP KERNEL
[ A1] MPYSU .M1 2,A1,A1 ; <0,15>
|| [!A1] STH .D2T2 B7,*++B5(4) ; |176| <0,15>
|| [ B0] B .S1 L11 ; |177| <2,11>
|| [ B0] SUB .S2 B0,1,B0 ; |177| <3,9>
|| LDW .D1T1 *A3++,A8 ; |175| <7,1>
[!A1] STH .D1T1 A6,*++A5(4) ; |175| <0,16>
|| SHR .S1 A7,16,A6 ; |175| <1,14>
|| SHR .S2 B8,16,B7 ; |176| <1,14>
|| SPINT .L1 A4,A7 ; |175| <3,10>
|| SPINT .L2 B7,B8 ; |176| <3,10>
|| MPYSP .M1 A0,A8,A4 ; |175| <5,6>
|| MPYSP .M2X A0,B6,B7 ; |176| <5,6>
|| LDW .D2T2 *B4++,B6 ; |176| <8,0>
;** --------------------------------------------------------------------------*
L12: ; PIPED LOOP EPILOG
MV .S2 B11,B3 ; |211|
|| LDW .D1T1 *A3++,A8 ; |175| (E) <8,1>
|| STH .D2T2 B7,*++B5(4) ; |176| (E) <1,15>
ZERO .D2 B4 ; |195|
|| STH .D1T1 A6,*++A5(4) ; |175| (E) <1,16>
|| SHR .S2 B8,16,B7 ; |176| (E) <2,14>
|| SPINT .L1 A4,A6 ; |175| (E) <4,10>
|| SPINT .L2 B7,B8 ; |176| (E) <4,10>
|| MPYSP .M1 A0,A8,A4 ; |175| (E) <6,6>
|| MPYSP .M2X A0,B6,B7 ; |176| (E) <6,6>
|| SHR .S1 A7,16,A3 ; |175| (E) <2,14>
STH .D2T2 B7,*++B5(4) ; |176| (E) <2,15>
STH .D1T1 A3,*++A5(4) ; |175| (E) <2,16>
|| SHR .S2 B8,16,B7 ; |176| (E) <3,14>
|| SPINT .L1 A4,A4 ; |175| (E) <5,10>
|| SPINT .L2 B7,B7 ; |176| (E) <5,10>
|| MPYSP .M1 A0,A8,A0 ; |175| (E) <7,6>
|| MPYSP .M2X A0,B6,B6 ; |176| (E) <7,6>
|| SHR .S1 A7,16,A3 ; |175| (E) <3,14>
STH .D2T2 B7,*++B5(4) ; |176| (E) <3,15>
STH .D1T1 A3,*++A5(4) ; |175| (E) <3,16>
|| SHR .S2 B8,16,B6 ; |176| (E) <4,14>
|| SPINT .L1 A4,A4 ; |175| (E) <6,10>
|| SPINT .L2 B7,B7 ; |176| (E) <6,10>
|| MPYSP .M1 A0,A8,A0 ; |175| (E) <8,6>
|| MPYSP .M2X A0,B6,B6 ; |176| (E) <8,6>
|| SHR .S1 A6,16,A3 ; |175| (E) <4,14>
STH .D2T2 B6,*++B5(4) ; |176| (E) <4,15>
STH .D1T1 A3,*++A5(4) ; |175| (E) <4,16>
|| SHR .S2 B7,16,B6 ; |176| (E) <5,14>
|| SPINT .L1 A0,A3 ; |175| (E) <7,10>
|| SPINT .L2 B6,B6 ; |176| (E) <7,10>
|| SHR .S1 A4,16,A3 ; |175| (E) <5,14>
STH .D2T2 B6,*++B5(4) ; |176| (E) <5,15>
STH .D1T1 A3,*++A5(4) ; |175| (E) <5,16>
|| SHR .S2 B7,16,B6 ; |176| (E) <6,14>
|| SPINT .L1 A0,A3 ; |175| (E) <8,10>
|| SPINT .L2 B6,B6 ; |176| (E) <8,10>
|| SHR .S1 A4,16,A0 ; |175| (E) <6,14>
STH .D2T2 B6,*++B5(4) ; |176| (E) <6,15>
STH .D1T1 A0,*++A5(4) ; |175| (E) <6,16>
|| SHR .S2 B6,16,B6 ; |176| (E) <7,14>
|| SHR .S1 A3,16,A0 ; |175| (E) <7,14>
MVC .S2 B9,CSR ; interrupts on
|| STH .D2T2 B6,*++B5(4) ; |176| (E) <7,15>
SHR .S1 A3,16,A0 ; |175| (E) <8,14>
|| STH .D1T1 A0,*++A5(4) ; |175| (E) <7,16>
|| SHR .S2 B6,16,B6 ; |176| (E) <8,14>
STH .D2T2 B6,*++B5(4) ; |176| (E) <8,15>
STH .D1T1 A0,*++A5(4) ; |175| (E) <8,16>
LDH .D2T2 *+DP(_ready_index),B5 ; |194|
LDDW .D2T2 *+SP(16),B11:B10 ; |211|
RET .S2 B3 ; |211|
|| LDDW .D2T1 *+SP(8),A11:A10 ; |211|
LDW .D2T1 *++SP(24),A12 ; |211|
STH .D2T2 B4,*+DP(_buffer_ready) ; |195|
NOP 3
; BRANCH OCCURS ; |211|
.sect ".text"
.global _IsOverRun
;******************************************************************************
;* FUNCTION NAME: _IsOverRun *
;* *
;* Regs Modified : A4 *
;* Regs Used : A4,B3,DP *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_IsOverRun:
;** --------------------------------------------------------------------------*
RET .S2 B3 ; |243|
LDH .D2T1 *+DP(_over_run),A4 ; |242|
NOP 4
; BRANCH OCCURS ; |243|
.sect ".text"
.global _IsBufferReady
;******************************************************************************
;* FUNCTION NAME: _IsBufferReady *
;* *
;* Regs Modified : A4 *
;* Regs Used : A4,B3,DP *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_IsBufferReady:
;** --------------------------------------------------------------------------*
RET .S2 B3 ; |227|
LDH .D2T1 *+DP(_buffer_ready),A4 ; |226|
NOP 4
; BRANCH OCCURS ; |227|
.sect ".text"
.global _EDMA_ISR
;******************************************************************************
;* FUNCTION NAME: _EDMA_ISR *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,DP *
;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
;******************************************************************************
_EDMA_ISR:
;** --------------------------------------------------------------------------*
MVKL .S1 0x8000,A0 ; |581|
|| MVKL .S2 0x1a0ffe4,B4 ; |581|
MVKH .S1 0x8000,A0 ; |581|
|| MVKH .S2 0x1a0ffe4,B4 ; |581|
STW .D2T1 A0,*B4 ; |581|
LDH .D2T2 *+DP(_ready_index),B4 ; |262|
MVK .S1 1,A0 ; |267|
MVKL .S1 _processBufferSwi,A4 ; |270|
MVKH .S1 _processBufferSwi,A4 ; |270|
NOP 1
ADD .D2 1,B4,B4 ; |262|
EXT .S2 B4,16,16,B5 ; |262|
ZERO .S2 B4 ; |265|
|| CMPLT .L2 B5,3,B0 ; |262|
|| STH .D2T2 B4,*+DP(_ready_index) ; |262|
[!B0] STH .D2T2 B4,*+DP(_ready_index) ; |265|
LDH .D2T2 *+DP(_buffer_ready),B4 ; |266|
NOP 1
CALLRET .S1 _SWI_post ; |270|
NOP 2
CMPEQ .L2 B4,1,B0 ; |266|
MVK .S2 1,B4 ; |268|
|| [ B0] STH .D2T1 A0,*+DP(_over_run) ; |267|
STH .D2T2 B4,*+DP(_buffer_ready) ; |268|
RL3: ; CALL OCCURS ; |271| ; bypass _EDMA_ISR upon return
;******************************************************************************
;* MARK THE END OF THE SCALAR INIT RECORD IN CINIT:C *
;******************************************************************************
CIR: .sect ".cinit:c"
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES *
;******************************************************************************
.global _SWI_post
.global _SINE_init
.global _sineGen
.global _processBufferSwi