;******************************************************************************
;* TMS320C6x ANSI C Codegen                   Version 4.10 Beta (May  4 2001) *
;* Date/Time created: Tue May 29 12:11:59 2001                                *
;******************************************************************************

;******************************************************************************
;* GLOBAL FILE PARAMETERS                                                     *
;*                                                                            *
;*   Architecture      : TMS320C671x                                          *
;*   Optimization      : Enabled at level 3                                   *
;*   Optimizing for    : Speed                                                *
;*                       Based on options: -o3, no -ms                        *
;*   Endian            : Little                                               *
;*   Interrupt Thrshld : Disabled                                             *
;*   Memory Model      : Large                                                *
;*   Calls to RTS      : Far                                                  *
;*   Pipelining        : Enabled                                              *
;*   Speculative Load  : Disabled                                             *
;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
;*   Debug Info        : No Debug Info                                        *
;*                                                                            *
;******************************************************************************

	.asg	A15, FP
	.asg	B14, DP
	.asg	B15, SP
	.global	$bss

_page_buffer:	.usect	.far,128,4

	.sect	".cinit"
	.align	8
	.field  	4,32
	.field  	_initialized$1+0,32
	.field  	0,32			; _initialized$1 @ 0
	.sect	".text"
_initialized$1:	.usect	.far,4,4
;	c:\ti\c6000\cgtools\bin\opt6x.exe -qq -v6711 -O3 C:\WINDOWS\TEMP\TI506495_2 C:\WINDOWS\TEMP\TI506495_4 
	.sect	".text:__FLASH_init"
	.clink
	.global	__FLASH_init

;******************************************************************************
;* FUNCTION NAME: __FLASH_init                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
;*                           B5,B6,B7,B8,B9,SP                                *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
;*                           B5,B6,B7,B8,B9,SP                                *
;*   Local Frame Size  : 0 Args + 0 Auto + 12 Save = 12 byte                  *
;******************************************************************************
__FLASH_init:
;** --------------------------------------------------------------------------*
           MVKL    .S1     _initialized$1,A0 ; |123| 
           MVKH    .S1     _initialized$1,A0 ; |123| 
           LDW     .D1T1   *A0,A1            ; |123| 
           MVKL    .S2     __BOARD_init,B4   ; |124| 
           MVKH    .S2     __BOARD_init,B4   ; |124| 
           NOP             2
   [ A1]   B       .S1     L1                ; |123| 
           STW     .D2T1   A11,*SP--(16)     ; |120| 

           MVKL    .S2     RL0,B3            ; |124| 
||         STW     .D2T2   B3,*+SP(12)       ; |120| 
||         MVK     .S1     1,A11             ; |125| 

           MVKL    .S1     _initialized$1,A10 ; |125| 
||         STW     .D2T1   A10,*+SP(8)       ; |120| 

           MVKH    .S1     _initialized$1,A10 ; |125| 
|| [ A1]   LDW     .D2T2   *+SP(12),B3       ; |127| 
||         MVKH    .S2     RL0,B3            ; |124| 

           NOP             1
           ; BRANCH OCCURS                   ; |123| 
;** --------------------------------------------------------------------------*
           B       .S2     B4                ; |124| 
           NOP             5
RL0:       ; CALL OCCURS                     ; |124| 
           STW     .D1T1   A11,*A10          ; |125| 
           LDW     .D2T2   *+SP(12),B3       ; |127| 
           NOP             1
;** --------------------------------------------------------------------------*
L1:    
           LDW     .D2T1   *+SP(8),A10       ; |127| 
           LDW     .D2T1   *++SP(16),A11     ; |127| 
           NOP             1
           B       .S2     B3                ; |127| 
           NOP             5
           ; BRANCH OCCURS                   ; |127| 


	.sect	".text:_validate_FLASH"
	.clink

;******************************************************************************
;* FUNCTION NAME: _validate_FLASH                                             *
;*                                                                            *
;*   Regs Modified     : A0,A1,A3,A4,A5,B4,B5                                 *
;*   Regs Used         : A0,A1,A3,A4,A5,B3,B4,B5                              *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_validate_FLASH:
;** --------------------------------------------------------------------------*

           ZERO    .D2     B5                ; |76| 
||         ZERO    .D1     A0                ; |76| 

           MVKH    .S2     0x90000000,B5     ; |76| 
||         MVKH    .S1     0x90020000,A0     ; |76| 

           B       .S2     B3                ; |81| 
||         ZERO    .D1     A0                ; |74| 
||         CMPLTU  .L1     A4,A0,A3
||         ADD     .S1X    B4,A4,A5

           MVKH    .S1     0x70000000,A0     ; |74| 
||         XOR     .L1     1,A3,A3           ; |76| 
||         CMPLTU  .L2X    A4,B5,B5
||         ZERO    .D2     B4                ; |76| 

           ADD     .D1     A0,A5,A0          ; |74| 
||         OR      .L2X    A3,B5,B5          ; |76| 
||         MVKH    .S2     0x20000,B4        ; |76| 

           XOR     .S2     1,B5,B4           ; |76| 
||         CMPGTU  .L1X    A0,B4,A1          ; |76| 

   [ A1]   ZERO    .D2     B4                ; |78| 
           MV      .S1X    B4,A4             ; |80| 
           ; BRANCH OCCURS                   ; |81| 


	.sect	".text:_FLASH_write"
	.clink
	.global	_FLASH_write

;******************************************************************************
;* FUNCTION NAME: _FLASH_write                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,B0,B1, *
;*                           B2,B3,B4,B5,B6,B7,B8,B9,SP                       *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,B0,B1, *
;*                           B2,B3,B4,B5,B6,B7,B8,B9,SP                       *
;*   Local Frame Size  : 0 Args + 4 Auto + 20 Save = 24 byte                  *
;******************************************************************************
_FLASH_write:
;** --------------------------------------------------------------------------*

           MVKL    .S1     0x1800004,A3      ; |255| 
||         MV      .L1X    B4,A8

           EXTU    .S1     A8,25,25,A2       ; |66| 
||         STW     .D2T1   A13,*SP--(24)     ; |253| 

           MV      .D1     A2,A1
||         STW     .D2T1   A10,*+SP(8)       ; |253| 
||         MVKH    .S1     0x1800004,A3      ; |255| 
||         MVK     .S2     128,B6            ; |66| 

           LDW     .D1T1   *A3,A10           ; |255| 
|| [!A2]   CMPLTU  .L1X    A6,B6,A1

   [!A1]   B       .S1     L3                ; |66| 

           MVKL    .S2     0x1800004,B4      ; |268| 
||         ZERO    .D2     B5                ; |100| 

           STW     .D2T1   A12,*+SP(16)      ; |253| 
||         MVKH    .S2     0x70000000,B5     ; |100| 
||         ZERO    .D1     A4                ; |100| 
||         MVKL    .S1     _page_buffer,A0   ; |101| 
||         MV      .L1     A4,A7

           STW     .D2T1   A11,*+SP(12)      ; |253| 
||         ADD     .L2X    B5,A8,B5          ; |100| 
||         MVKH    .S2     0x1800004,B4      ; |268| 
||         MVKH    .S1     0x70000000,A4     ; |100| 

           CLR     .S1     A10,4,7,A3        ; |268| 
||         CLR     .S2     B5,0,6,B5         ; |100| 
||         STW     .D2T2   B3,*+SP(20)       ; |253| 

           SUB     .L1X    B5,A4,A3          ; |100| 
||         STW     .D2T1   A3,*B4            ; |268| 
||         MVKH    .S1     _page_buffer,A0   ; |101| 
||         MVK     .S2     0x80,B0           ; |103| 

           ; BRANCH OCCURS                   ; |66| 
;** --------------------------------------------------------------------------*
           SUB     .D2     B0,1,B0           ; |105| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 103
;*      Loop opening brace source line : 103
;*      Loop closing brace source line : 105
;*      Known Minimum Trip Count         : 128
;*      Known Maximum Trip Count         : 128
;*      Known Max Trip Count Factor      : 128
;*      Loop Carried Dependency Bound(^) : 7
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1*       0     
;*      .D units                     1*       1*    
;*      .M units                     0        0     
;*      .X cross paths               0        1*    
;*      .T address paths             1*       1*    
;*      Long read paths              0        1*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        1     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1*       1*    
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L2:    

   [ B0]   B       .S1     L2                ; |105| 
||         LDB     .D1T1   *A3++,A4          ; |104| 

   [ B0]   SUB     .D2     B0,1,B0           ; |105| 
           NOP             3
           STB     .D1T1   A4,*A0++          ; |104| 
           ; BRANCH OCCURS                   ; |105| 
;** --------------------------------------------------------------------------*
L3:    
           ADD     .D1     A2,A6,A3
           CMPLTU  .L1     A2,A3,A1
   [!A1]   B       .S1     L6                ; |281| 
           MVKL    .S1     _page_buffer-1,A0
           MVKH    .S1     _page_buffer-1,A0

           ADD     .D1     A0,A2,A0
||         MV      .S1     A2,A9
||         MV      .L2X    A6,B0             ; |282| 
|| [!A1]   MVKL    .S2     _validate_FLASH,B5 ; |289| 

   [!A1]   MVKH    .S2     _validate_FLASH,B5 ; |289| 
|| [ A1]   ADD     .D1     1,A2,A3           ; |65| 

   [ A1]   EXTU    .S1     A3,25,25,A1       ; |65| 
           ; BRANCH OCCURS                   ; |281| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*      Disqualified loop: bad loop structure
;*----------------------------------------------------------------------------*
L4:    

   [!A1]   B       .S1     L5                ; |66| 
||         LDB     .D1T1   *A7++,A4          ; |282| 

           ADD     .S1     1,A2,A2           ; |284| 
   [ A1]   SUB     .D2     B0,1,B0           ; |286| 
   [!A1]   MVKL    .S2     _validate_FLASH,B5 ; |289| 
           NOP             1
           STB     .D1T1   A4,*++A0          ; |282| 
           ; BRANCH OCCURS                   ; |66| 
;** --------------------------------------------------------------------------*
   [ B0]   B       .S1     L4                ; |286| 
   [ B0]   ADD     .D1     1,A2,A3           ; |65| 
   [!B0]   MVKL    .S2     _validate_FLASH,B5 ; |289| 
   [ B0]   EXTU    .S1     A3,25,25,A1       ; |65| 
           NOP             2
           ; BRANCH OCCURS                   ; |286| 
;** --------------------------------------------------------------------------*
L5:    
           MVKH    .S2     _validate_FLASH,B5 ; |289| 
;** --------------------------------------------------------------------------*
L6:    
           B       .S2     B5                ; |289| 
           MVKL    .S2     RL2,B3            ; |289| 
           MVKH    .S2     RL2,B3            ; |289| 
           MV      .L2X    A6,B4             ; |289| 
           MV      .D1     A8,A4             ; |289| 
           NOP             1
RL2:       ; CALL OCCURS                     ; |289| 

           ZERO    .D1     A5                ; |293| 
||         MVKL    .S1     _page_buffer-4,A3

           MVKH    .S1     0x70000000,A5     ; |293| 
           MVKL    .S1     0x90005555,A11    ; |85| 

           MVK     .S2     85,B6             ; |86| 
||         MV      .D1     A4,A1             ; |289| 
||         MVKL    .S1     0x90005555,A0     ; |87| 

           MVKH    .S1     _page_buffer-4,A3
||         ADD     .D1     A5,A8,A5          ; |293| 
|| [!A1]   B       .S2     L13               ; |289| 

           MVK     .S2     0x20,B0           ; |294| 
||         CLR     .S1     A5,0,6,A5         ; |293| 

           MVKL    .S2     0x90002aaa,B5     ; |86| 
||         MVK     .S1     -86,A12           ; |85| 

           MVKL    .S2     0x8ffffffc,B4     ; |293| 
||         MVK     .S1     -96,A13           ; |87| 

           SUB     .D1     A2,A9,A2          ; |287| 
||         MVKH    .S2     0x8ffffffc,B4     ; |293| 
||         MVKH    .S1     0x90005555,A11    ; |85| 

           ADD     .L1X    B4,A5,A3          ; |293| 
|| [!A1]   LDW     .D2T2   *+SP(20),B3       ; |311| 
||         MVKH    .S1     0x90005555,A0     ; |87| 
||         MVKH    .S2     0x90002aaa,B5     ; |86| 
||         MV      .D1     A3,A4

           ; BRANCH OCCURS                   ; |289| 
;** --------------------------------------------------------------------------*
           STB     .D1T1   A12,*A11          ; |85| 

           ADD     .S2X    1,A3,B4
||         STB     .D2T2   B6,*B5            ; |86| 

           ADD     .S2X    1,A4,B6
||         STB     .D1T1   A13,*A0           ; |87| 

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 294
;*      Loop opening brace source line : 294
;*      Loop closing brace source line : 296
;*      Loop Unroll Multiple             : 4x
;*      Known Minimum Trip Count         : 32
;*      Known Maximum Trip Count         : 32
;*      Known Max Trip Count Factor      : 32
;*      Loop Carried Dependency Bound(^) : 24
;*      Unpartitioned Resource Bound     : 4
;*      Partitioned Resource Bound(*)    : 6
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     0        1     
;*      .D units                     6*       2     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             6*       2     
;*      Long read paths              3        1     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             0        1     
;*      Bound(.L .S .D .LS .LSD)     3        2     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 24 Schedule found with 1 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 0
;*      Collapsed prolog stages     : 0
;*
;*      Minimum safe trip count     : 1 (after unrolling)
;*----------------------------------------------------------------------------*
L7:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L8:    ; PIPED LOOP KERNEL
           LDB     .D1T1   *++A4(4),A0       ;  ^ |295| 
           NOP             4
           STB     .D1T1   A0,*++A3(4)       ;  ^ |295| 

           ADD     .D1     1,A3,A5           ; |295| 
||         LDB     .D2T2   *++B6(4),B5       ;  ^ |295| 

           NOP             4
           STB     .D2T2   B5,*++B4(4)       ;  ^ |295| 
           LDB     .D1T1   *+A4(2),A0        ;  ^ |295| 
           NOP             4

   [ B0]   SUB     .D2     B0,1,B0           ; |296| 
||         STB     .D1T1   A0,*+A3(2)        ;  ^ |295| 

   [ B0]   B       .S2     L8                ; |296| 
||         LDB     .D1T1   *+A4(3),A0        ;  ^ |295| 

           NOP             4
           STB     .D1T1   A0,*+A3(3)        ;  ^ |295| 
;** --------------------------------------------------------------------------*
L9:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*

           MVKL    .S1     _page_buffer+127,A0 ; |300| 
||         ADD     .D1     4,A3,A3

           MVKH    .S1     _page_buffer+127,A0 ; |300| 
||         LDB     .D1T1   *--A3,A4          ; |298| 

           LDB     .D1T1   *A0,A0            ; |300| 
           NOP             3
           STB     .D2T1   A4,*+SP(4)        ; |298| 

           LDB     .D2T2   *+SP(4),B5        ; |300| 
||         MV      .S2X    A0,B4

           NOP             4
           CMPEQ   .L1X    B5,A0,A1          ; |300| 
   [ A1]   B       .S2     L12               ; |300| 
   [ A1]   CMPLTU  .L1     A2,A6,A1          ; |304| 
           NOP             4
           ; BRANCH OCCURS                   ; |300| 
;** --------------------------------------------------------------------------*
           LDB     .D1T1   *A3,A0            ; |301| 
           NOP             4
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 300
;*      Loop opening brace source line : 300
;*      Loop closing brace source line : 302
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 13
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        1     
;*      .S units                     1        0     
;*      .D units                     1        2*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             2*       1     
;*      Long read paths              1        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          4        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L10:    
           STB     .D2T1   A0,*+SP(4)        ; |301| 
           LDB     .D2T2   *+SP(4),B5        ; |302| 
           NOP             4
           CMPEQ   .L2     B5,B4,B0          ; |302| 
   [!B0]   B       .S1     L10               ; |302| 
   [!B0]   LDB     .D1T1   *A3,A0            ; |301| 
           NOP             4
           ; BRANCH OCCURS                   ; |302| 
;** --------------------------------------------------------------------------*
L11:    
           CMPLTU  .L1     A2,A6,A1          ; |304| 
;** --------------------------------------------------------------------------*
L12:    
   [!A1]   B       .S1     L14               ; |304| 
           MVKL    .S2     RL4,B3            ; |305| 
           MVKL    .S2     _FLASH_write,B5   ; |305| 
           MVKH    .S2     RL4,B3            ; |305| 

           MVKH    .S2     _FLASH_write,B5   ; |305| 
||         SUB     .D1     A6,A2,A6
||         MV      .S1     A7,A4
|| [!A1]   LDW     .D2T2   *+SP(20),B3       ; |311| 

           NOP             1
           ; BRANCH OCCURS                   ; |304| 
;** --------------------------------------------------------------------------*
           B       .S2     B5                ; |305| 
           ADD     .S2X    3,A5,B4
           NOP             4
RL4:       ; CALL OCCURS                     ; |305| 
           LDW     .D2T2   *+SP(20),B3       ; |311| 
;** --------------------------------------------------------------------------*
L13:    
           NOP             1
;** --------------------------------------------------------------------------*
L14:    

           LDW     .D2T1   *+SP(16),A12      ; |311| 
||         MVKL    .S1     0x1800004,A0      ; |310| 

           LDW     .D2T1   *+SP(12),A11      ; |311| 
||         MVKH    .S1     0x1800004,A0      ; |310| 

           STW     .D1T1   A10,*A0           ; |310| 

           B       .S2     B3                ; |311| 
||         LDW     .D2T1   *+SP(8),A10       ; |311| 

           LDW     .D2T1   *++SP(24),A13     ; |311| 
           NOP             4
           ; BRANCH OCCURS                   ; |311| 


	.sect	".text:_FLASH_read"
	.clink
	.global	_FLASH_read

;******************************************************************************
;* FUNCTION NAME: _FLASH_read                                                 *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B3,B4,B5,B6,B9      *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B3,B4,B5,B6,B9      *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_FLASH_read:
;** --------------------------------------------------------------------------*
           MVKL    .S1     0x1800004,A0      ; |233| 

           MVKH    .S1     0x1800004,A0      ; |233| 
||         MVKL    .S2     _validate_FLASH,B6 ; |245| 

           LDW     .D1T1   *A0,A9            ; |233| 
||         MVKH    .S2     _validate_FLASH,B6 ; |245| 

           B       .S2     B6                ; |245| 
           MVKL    .S2     0x1800004,B5      ; |242| 
           MV      .D2     B3,B9             ; |231| 
           MVKL    .S2     RL6,B3            ; |245| 

           CLR     .S1     A9,4,7,A0         ; |242| 
||         MVKH    .S2     0x1800004,B5      ; |242| 

           STW     .D2T1   A0,*B5            ; |242| 
||         MVKH    .S2     RL6,B3            ; |245| 
||         MV      .L2X    A6,B4
||         MV      .D1     A4,A8
||         MV      .S1X    B4,A7

RL6:       ; CALL OCCURS                     ; |245| 
           MV      .D1     A4,A2

   [!A2]   MV      .D1     A2,A6             ; |245| 
||         MV      .S2X    A6,B0

           MV      .D1     A6,A1             ; |245| 
   [!A1]   B       .S1     L16               ; |245| 
   [ A1]   SUB     .D2     B0,1,B0           ; |247| 
           NOP             4
           ; BRANCH OCCURS                   ; |245| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 247
;*      Loop opening brace source line : 247
;*      Loop closing brace source line : 247
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 7
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1*       0     
;*      .D units                     1*       1*    
;*      .M units                     0        0     
;*      .X cross paths               0        1*    
;*      .T address paths             1*       1*    
;*      Long read paths              0        1*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        1     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1*       1*    
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L15:    

   [ B0]   B       .S1     L15               ; |247| 
||         LDB     .D1T1   *A8++,A0          ; |247| 

   [ B0]   SUB     .D2     B0,1,B0           ; |247| 
           NOP             3
           STB     .D1T1   A0,*A7++          ; |247| 
           ; BRANCH OCCURS                   ; |247| 
;** --------------------------------------------------------------------------*
L16:    
           B       .S2     B9                ; |251| 
           MVKL    .S1     0x1800004,A0      ; |250| 
           MVKH    .S1     0x1800004,A0      ; |250| 
           STW     .D1T1   A9,*A0            ; |250| 
           NOP             2
           ; BRANCH OCCURS                   ; |251| 


	.sect	".text:_FLASH_erase"
	.clink
	.global	_FLASH_erase

;******************************************************************************
;* FUNCTION NAME: _FLASH_erase                                                *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2,  *
;*                           B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,SP              *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2,  *
;*                           B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,SP              *
;*   Local Frame Size  : 0 Args + 4 Auto + 28 Save = 32 byte                  *
;******************************************************************************
_FLASH_erase:
;** --------------------------------------------------------------------------*

           MVKL    .S1     0x1800004,A0      ; |159| 
||         MV      .D1     A4,A6

           EXTU    .S1     A6,25,25,A2       ; |66| 
||         STW     .D2T2   B12,*SP--(32)     ; |157| 

           MVKH    .S1     0x1800004,A0      ; |159| 
||         STW     .D2T1   A10,*+SP(8)       ; |157| 

           MVK     .S1     128,A0            ; |66| 
||         LDW     .D1T1   *A0,A10           ; |159| 
||         MV      .L1     A2,A1

   [!A2]   CMPLTU  .L1X    B4,A0,A1
||         MVKL    .S2     _page_buffer,B7   ; |101| 

   [!A1]   B       .S1     L18               ; |66| 
||         STW     .D2T2   B10,*+SP(24)      ; |157| 
||         MVKL    .S2     0x1800004,B5      ; |173| 
||         ZERO    .L2     B6                ; |100| 

           STW     .D2T2   B3,*+SP(20)       ; |157| 
||         MVKH    .S2     0x70000000,B6     ; |100| 

           STW     .D2T1   A12,*+SP(16)      ; |157| 
||         MVKH    .S2     _page_buffer,B7   ; |101| 
||         ZERO    .D1     A4                ; |100| 
||         MVKL    .S1     0x9001ffff,A5     ; |165| 

           STW     .D2T1   A11,*+SP(12)      ; |157| 
||         ADD     .L2X    B6,A6,B6          ; |100| 
||         MVKH    .S1     0x70000000,A4     ; |100| 
||         MVKH    .S2     0x1800004,B5      ; |173| 

           MV      .L1X    B7,A0             ; |101| 
||         CLR     .S2     B6,0,6,B4         ; |100| 
||         CLR     .S1     A10,4,7,A3        ; |173| 
||         STW     .D2T2   B11,*+SP(28)      ; |157| 
||         MV      .L2     B4,B8

           SUB     .L1X    B4,A4,A3          ; |100| 
||         STW     .D2T1   A3,*B5            ; |173| 
||         MVKH    .S1     0x9001ffff,A5     ; |165| 
||         MVK     .S2     0x80,B0           ; |103| 

           ; BRANCH OCCURS                   ; |66| 
;** --------------------------------------------------------------------------*
           SUB     .D2     B0,1,B0           ; |105| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 103
;*      Loop opening brace source line : 103
;*      Loop closing brace source line : 105
;*      Known Minimum Trip Count         : 128
;*      Known Maximum Trip Count         : 128
;*      Known Max Trip Count Factor      : 128
;*      Loop Carried Dependency Bound(^) : 7
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     1*       0     
;*      .D units                     1*       1*    
;*      .M units                     0        0     
;*      .X cross paths               0        1*    
;*      .T address paths             1*       1*    
;*      Long read paths              0        1*    
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        1     (.L or .S unit)
;*      Addition ops (.LSD)          0        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1*       1*    
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L17:    

   [ B0]   B       .S1     L17               ; |105| 
||         LDB     .D1T1   *A3++,A4          ; |104| 

   [ B0]   SUB     .D2     B0,1,B0           ; |105| 
           NOP             3
           STB     .D1T1   A4,*A0++          ; |104| 
           ; BRANCH OCCURS                   ; |105| 
;** --------------------------------------------------------------------------*
L18:    
           ADD     .S1X    A2,B8,A3
           CMPLTU  .L1     A2,A3,A1
   [!A1]   B       .S1     L20               ; |186| 
           MVKL    .S1     _page_buffer-1,A0

           MV      .S2X    A2,B10
||         MVKH    .S1     _page_buffer-1,A0

           MVK     .S1     0xffffffff,A3
||         ADD     .D1     A0,A2,A0
||         MV      .L2X    A2,B7
||         MV      .D2     B8,B0             ; |187| 
|| [!A1]   MVKL    .S2     _validate_FLASH,B6 ; |207| 

   [!A1]   MVKL    .S2     0x90002aaa,B9     ; |95| 
|| [!A1]   MVK     .S1     -1,A3             ; |194| 

   [!A1]   MVKL    .S2     0x90005555,B2     ; |93| 
|| [!A1]   MVKL    .S1     0x90005555,A11    ; |94| 
|| [ A1]   ADD     .D2     1,B7,B4           ; |65| 

           ; BRANCH OCCURS                   ; |186| 
;** --------------------------------------------------------------------------*
           EXTU    .S2     B4,25,25,B1       ; |65| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*      Disqualified loop: bad loop structure
;*----------------------------------------------------------------------------*
L19:    
   [!B1]   B       .S1     L21               ; |66| 

           ADD     .D2     1,B7,B7           ; |189| 
||         STB     .D1T1   A3,*++A0          ; |187| 
|| [ B1]   SUB     .L2     B0,1,B0           ; |191| 
|| [!B1]   MVKL    .S2     _validate_FLASH,B6 ; |207| 

   [!B1]   MVKL    .S2     0x90002aaa,B9     ; |95| 
|| [!B1]   MVK     .S1     -1,A3             ; |194| 

   [!B1]   MVKL    .S2     0x90005555,B2     ; |93| 
|| [!B1]   MVKL    .S1     0x90005555,A11    ; |94| 

   [!B1]   MVKL    .S2     0x90002aaa,B0     ; |92| 
|| [!B1]   MVKL    .S1     0x90005555,A8     ; |85| 

   [!B1]   MVKL    .S2     RL8,B3            ; |207| 
|| [!B1]   MVKL    .S1     0x90005555,A2     ; |96| 

           ; BRANCH OCCURS                   ; |66| 
;** --------------------------------------------------------------------------*
   [ B0]   B       .S1     L19               ; |191| 
   [ B0]   ADD     .D2     1,B7,B4           ; |65| 
   [!B0]   MVKL    .S2     _validate_FLASH,B6 ; |207| 
   [ B0]   EXTU    .S2     B4,25,25,B1       ; |65| 

   [!B0]   MVKL    .S2     0x90002aaa,B9     ; |95| 
|| [!B0]   MVK     .S1     -1,A3             ; |194| 

   [!B0]   MVKL    .S2     0x90005555,B2     ; |93| 
|| [!B0]   MVKL    .S1     0x90005555,A11    ; |94| 

           ; BRANCH OCCURS                   ; |191| 
;** --------------------------------------------------------------------------*
L20:    

           MVKL    .S2     0x90002aaa,B0     ; |92| 
||         MVKL    .S1     0x90005555,A8     ; |85| 

           MVKL    .S2     RL8,B3            ; |207| 
||         MVKL    .S1     0x90005555,A2     ; |96| 

;** --------------------------------------------------------------------------*
L21:    

           MVKL    .S2     0x90005555,B1     ; |87| 
||         MVKL    .S1     0x90002aaa,A7     ; |86| 

           MVK     .S2     -96,B11           ; |87| 
||         MVKL    .S1     0x90005555,A9     ; |91| 

           MVK     .S2     0x55,B5           ; |86| 
||         MVK     .S1     16,A12            ; |96| 

           MVK     .S1     0xffffffaa,A0     ; |85| 
||         CMPEQ   .L1X    B8,A3,A1          ; |194| 
||         MVK     .S2     -128,B12          ; |93| 

   [ A1]   B       .S1     L28               ; |194| 
||         MVKH    .S2     _validate_FLASH,B6 ; |207| 

           MVKH    .S2     0x90002aaa,B9     ; |95| 
||         MVKH    .S1     0x90005555,A11    ; |94| 

           MVKH    .S1     0x90005555,A8     ; |85| 
||         MVKH    .S2     0x90005555,B2     ; |93| 

           MVKH    .S1     0x90005555,A2     ; |96| 
||         MVKH    .S2     0x90002aaa,B0     ; |92| 

           MVKH    .S2     RL8,B3            ; |207| 
||         MVKH    .S1     0x90002aaa,A7     ; |86| 

           ZERO    .D1     A3                ; |196| 
||         MVKH    .S2     0x90005555,B1     ; |87| 
||         MVKH    .S1     0x90005555,A9     ; |91| 
||         MV      .L1     A6,A4             ; |207| 
||         MV      .D2     B8,B4             ; |207| 
||         SUB     .L2     B7,B10,B7         ; |192| 

           ; BRANCH OCCURS                   ; |194| 
;** --------------------------------------------------------------------------*
           B       .S2     B6                ; |207| 
           NOP             5
RL8:       ; CALL OCCURS                     ; |207| 
           ZERO    .D1     A8                ; |211| 
           MVKH    .S1     0x70000000,A8     ; |211| 
           MVK     .S1     -86,A7            ; |85| 

           ADD     .D1     A8,A6,A6          ; |211| 
||         MVK     .S1     -96,A9            ; |87| 

           MVK     .S2     0x20,B0           ; |213| 
||         MV      .D1     A4,A1             ; |207| 
||         CLR     .S1     A6,0,6,A6         ; |211| 

           MVKL    .S1     _page_buffer-4,A3
|| [!A1]   B       .S2     L31               ; |207| 

           MVK     .S2     85,B6             ; |86| 
||         MVKL    .S1     0x90005555,A0     ; |85| 

           MVKL    .S2     0x8ffffffc,B5     ; |211| 
||         MVKL    .S1     0x90005555,A5     ; |87| 

           MVKH    .S1     _page_buffer-4,A3
||         MVKH    .S2     0x8ffffffc,B5     ; |211| 

           MVKL    .S2     0x90002aaa,B4     ; |86| 
||         MVKH    .S1     0x90005555,A0     ; |85| 

           ADD     .L1X    B5,A6,A3          ; |211| 
|| [!A1]   LDW     .D2T2   *+SP(20),B3       ; |229| 
||         MVKH    .S1     0x90005555,A5     ; |87| 
||         MVKH    .S2     0x90002aaa,B4     ; |86| 
||         MV      .D1     A3,A4

           ; BRANCH OCCURS                   ; |207| 
;** --------------------------------------------------------------------------*
           STB     .D1T1   A7,*A0            ; |85| 

           STB     .D2T2   B6,*B4            ; |86| 
||         ADD     .S2X    1,A4,B6

           ADD     .S2X    1,A3,B4
||         STB     .D1T1   A9,*A5            ; |87| 

;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 213
;*      Loop opening brace source line : 213
;*      Loop closing brace source line : 216
;*      Loop Unroll Multiple             : 4x
;*      Known Minimum Trip Count         : 32
;*      Known Maximum Trip Count         : 32
;*      Known Max Trip Count Factor      : 32
;*      Loop Carried Dependency Bound(^) : 24
;*      Unpartitioned Resource Bound     : 4
;*      Partitioned Resource Bound(*)    : 6
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     0        1     
;*      .D units                     6*       2     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             6*       2     
;*      Long read paths              3        1     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             0        1     
;*      Bound(.L .S .D .LS .LSD)     3        2     
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 24 Schedule found with 1 iterations in parallel
;*      done
;*
;*      Loop is interruptible
;*      Collapsed epilog stages     : 0
;*      Collapsed prolog stages     : 0
;*
;*      Minimum safe trip count     : 1 (after unrolling)
;*----------------------------------------------------------------------------*
L22:    ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L23:    ; PIPED LOOP KERNEL
           LDB     .D1T1   *++A4(4),A0       ;  ^ |214| 
           NOP             4
           STB     .D1T1   A0,*++A3(4)       ;  ^ |214| 

           ADD     .D1     1,A3,A5           ; |214| 
||         LDB     .D2T2   *++B6(4),B5       ;  ^ |214| 

           NOP             4
           STB     .D2T2   B5,*++B4(4)       ;  ^ |214| 
           LDB     .D1T1   *+A4(2),A0        ;  ^ |214| 
           NOP             4

   [ B0]   SUB     .D2     B0,1,B0           ; |216| 
||         STB     .D1T1   A0,*+A3(2)        ;  ^ |214| 

   [ B0]   B       .S2     L23               ; |216| 
||         LDB     .D1T1   *+A4(3),A0        ;  ^ |214| 

           NOP             4
           STB     .D1T1   A0,*+A3(3)        ;  ^ |214| 
;** --------------------------------------------------------------------------*
L24:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*

           MVKL    .S1     _page_buffer+127,A0 ; |220| 
||         ADD     .D1     4,A3,A3

           MVKH    .S1     _page_buffer+127,A0 ; |220| 
||         LDB     .D1T1   *--A3,A4          ; |218| 

           LDB     .D1T1   *A0,A0            ; |220| 
           NOP             3
           STB     .D2T1   A4,*+SP(4)        ; |218| 

           LDB     .D2T2   *+SP(4),B5        ; |220| 
||         MV      .S2X    A0,B4

           NOP             4
           CMPEQ   .L1X    B5,A0,A1          ; |220| 
   [ A1]   B       .S2     L27               ; |220| 

   [ A1]   CMPLTU  .L2     B7,B8,B0          ; |224| 
|| [!A1]   LDB     .D1T1   *A3,A0            ; |221| 

           NOP             4
           ; BRANCH OCCURS                   ; |220| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 220
;*      Loop opening brace source line : 220
;*      Loop closing brace source line : 222
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 13
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        1     
;*      .S units                     1        0     
;*      .D units                     1        2*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             2*       1     
;*      Long read paths              1        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          4        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L25:    
           STB     .D2T1   A0,*+SP(4)        ; |221| 
           LDB     .D2T2   *+SP(4),B5        ; |222| 
           NOP             4
           CMPEQ   .L2     B5,B4,B0          ; |222| 
   [!B0]   B       .S1     L25               ; |222| 
   [!B0]   LDB     .D1T1   *A3,A0            ; |221| 
           NOP             4
           ; BRANCH OCCURS                   ; |222| 
;** --------------------------------------------------------------------------*
L26:    
           CMPLTU  .L2     B7,B8,B0          ; |224| 
;** --------------------------------------------------------------------------*
L27:    
   [!B0]   B       .S1     L30               ; |224| 
           MVKL    .S2     RL10,B3           ; |224| 
           MVKL    .S2     _FLASH_erase,B5   ; |224| 
           MVKH    .S2     RL10,B3           ; |224| 
           MVKH    .S2     _FLASH_erase,B5   ; |224| 
           SUB     .D2     B8,B7,B4
           ; BRANCH OCCURS                   ; |224| 
;** --------------------------------------------------------------------------*
           B       .S2     B5                ; |224| 
           ADD     .D1     3,A5,A4
           NOP             4
RL10:      ; CALL OCCURS                     ; |224| 
           B       .S1     L32               ; |224| 
           LDW     .D2T2   *+SP(20),B3       ; |229| 
           LDW     .D2T2   *+SP(24),B10      ; |229| 

           MVKL    .S1     0x1800004,A0      ; |228| 
||         LDW     .D2T1   *+SP(16),A12      ; |229| 

           MVKH    .S1     0x1800004,A0      ; |228| 
||         LDW     .D2T1   *+SP(12),A11      ; |229| 

           STW     .D1T1   A10,*A0           ; |228| 
||         LDW     .D2T2   *+SP(28),B11      ; |229| 

           ; BRANCH OCCURS                   ; |224| 
;** --------------------------------------------------------------------------*
L28:    
           STB     .D1T1   A0,*A8            ; |85| 
           STB     .D1T2   B5,*A7            ; |86| 
           STB     .D2T2   B11,*B1           ; |87| 
           STB     .D1T1   A3,*A5            ; |196| 
           STB     .D1T1   A0,*A9            ; |91| 
           STB     .D2T2   B5,*B0            ; |92| 
           STB     .D2T2   B12,*B2           ; |93| 
           STB     .D1T1   A0,*A11           ; |94| 
           STB     .D2T2   B5,*B9            ; |95| 
           STB     .D1T1   A12,*A2           ; |96| 
           LDB     .D1T1   *A5,A0            ; |201| 
           NOP             4
           STB     .D2T1   A0,*+SP(4)        ; |201| 
           LDB     .D2T2   *+SP(4),B4        ; |202| 
           NOP             4
           CMPEQ   .L2     B4,-1,B0          ; |202| 
   [ B0]   B       .S1     L32               ; |202| 
   [ B0]   LDW     .D2T2   *+SP(20),B3       ; |229| 
   [ B0]   LDW     .D2T2   *+SP(24),B10      ; |229| 

   [ B0]   LDW     .D2T1   *+SP(16),A12      ; |229| 
|| [ B0]   MVKL    .S1     0x1800004,A0      ; |228| 

   [ B0]   LDW     .D2T1   *+SP(12),A11      ; |229| 
|| [ B0]   MVKH    .S1     0x1800004,A0      ; |228| 

   [ B0]   STW     .D1T1   A10,*A0           ; |228| 
|| [ B0]   LDW     .D2T2   *+SP(28),B11      ; |229| 

           ; BRANCH OCCURS                   ; |202| 
;** --------------------------------------------------------------------------*
           LDB     .D1T1   *A5,A0            ; |203| 
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 202
;*      Loop opening brace source line : 202
;*      Loop closing brace source line : 204
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 13
;*      Unpartitioned Resource Bound     : 2
;*      Partitioned Resource Bound(*)    : 2
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        1     
;*      .S units                     1        0     
;*      .D units                     1        2*    
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             2*       1     
;*      Long read paths              1        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          4        0     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             1        1     
;*      Bound(.L .S .D .LS .LSD)     2*       1     
;*
;*      Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L29:    
           NOP             4
           STB     .D2T1   A0,*+SP(4)        ; |203| 
           LDB     .D2T2   *+SP(4),B4        ; |204| 
           NOP             4
           CMPEQ   .L2     B4,-1,B0          ; |204| 
   [!B0]   B       .S1     L29               ; |204| 
   [!B0]   LDB     .D1T1   *A5,A0            ; |203| 
           NOP             4
           ; BRANCH OCCURS                   ; |204| 
;** --------------------------------------------------------------------------*
L30:    
           LDW     .D2T2   *+SP(20),B3       ; |229| 
;** --------------------------------------------------------------------------*
L31:    
           LDW     .D2T2   *+SP(24),B10      ; |229| 

           LDW     .D2T1   *+SP(16),A12      ; |229| 
||         MVKL    .S1     0x1800004,A0      ; |228| 

           LDW     .D2T1   *+SP(12),A11      ; |229| 
||         MVKH    .S1     0x1800004,A0      ; |228| 

           STW     .D1T1   A10,*A0           ; |228| 
||         LDW     .D2T2   *+SP(28),B11      ; |229| 

;** --------------------------------------------------------------------------*
L32:    

           B       .S2     B3                ; |229| 
||         LDW     .D2T1   *+SP(8),A10       ; |229| 

           LDW     .D2T2   *++SP(32),B12     ; |229| 
           NOP             4
           ; BRANCH OCCURS                   ; |229| 


	.sect	".text:_FLASH_checksum"
	.clink
	.global	_FLASH_checksum

;******************************************************************************
;* FUNCTION NAME: _FLASH_checksum                                             *
;*                                                                            *
;*   Regs Modified     : A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B3,B4,B5,B6,B9         *
;*   Regs Used         : A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B3,B4,B5,B6,B9         *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_FLASH_checksum:
;** --------------------------------------------------------------------------*
           MVKL    .S1     0x1800004,A0      ; |131| 

           MVKH    .S1     0x1800004,A0      ; |131| 
||         MVKL    .S2     _validate_FLASH,B6 ; |144| 

           LDW     .D1T1   *A0,A6            ; |131| 
||         MVKH    .S2     _validate_FLASH,B6 ; |144| 

           B       .S2     B6                ; |144| 
           MVKL    .S2     0x1800004,B5      ; |139| 
           MV      .D2     B3,B9             ; |129| 
           MVKL    .S2     RL12,B3           ; |144| 

           CLR     .S1     A6,4,7,A0         ; |139| 
||         MVKH    .S2     0x1800004,B5      ; |139| 

           STW     .D2T1   A0,*B5            ; |139| 
||         MVKH    .S2     RL12,B3           ; |144| 
||         MV      .D1     A4,A7
||         MV      .S1X    B4,A2

RL12:      ; CALL OCCURS                     ; |144| 
           MV      .D1     A4,A1             ; |144| 
   [!A1]   B       .S1     L36               ; |144| 
           ZERO    .D1     A0                ; |145| 
   [!A1]   MVK     .S1     0xffffffff,A0     ; |143| 
           NOP             3
           ; BRANCH OCCURS                   ; |144| 
;** --------------------------------------------------------------------------*
   [!A2]   B       .S1     L36               ; |146| 
           MV      .S2X    A2,B4             ; |147| 
           NOP             4
           ; BRANCH OCCURS                   ; |146| 
;** --------------------------------------------------------------------------*
           MVK     .S2     0x4,B1            ; init prolog collapse predicate
;*----------------------------------------------------------------------------*
;*   SOFTWARE PIPELINE INFORMATION
;*
;*      Loop source line               : 146
;*      Loop opening brace source line : 146
;*      Loop closing brace source line : 148
;*      Known Minimum Trip Count         : 1
;*      Known Max Trip Count Factor      : 1
;*      Loop Carried Dependency Bound(^) : 0
;*      Unpartitioned Resource Bound     : 1
;*      Partitioned Resource Bound(*)    : 1
;*      Resource Partition:
;*                                A-side   B-side
;*      .L units                     0        0     
;*      .S units                     0        1*    
;*      .D units                     1*       0     
;*      .M units                     0        0     
;*      .X cross paths               0        0     
;*      .T address paths             1*       0     
;*      Long read paths              0        0     
;*      Long write paths             0        0     
;*      Logical  ops (.LS)           0        0     (.L or .S unit)
;*      Addition ops (.LSD)          1        1     (.L or .S or .D unit)
;*      Bound(.L .S .LS)             0        1*    
;*      Bound(.L .S .D .LS .LSD)     1*       1*    
;*
;*      Searching for software pipeline schedule at ...
;*         ii = 1  Schedule found with 7 iterations in parallel
;*      done
;*
;*      Collapsed epilog stages     : 6
;*      Prolog not entirely removed
;*      Collapsed prolog stages     : 4
;*
;*      Minimum required memory pad : 0 bytes
;*
;*      For further improvement on this loop, try option -mh5
;*
;*      Minimum safe trip count     : 1
;*----------------------------------------------------------------------------*
L33:    ; PIPED LOOP PROLOG
           B       .S2     L34               ; (P) |148| 
           B       .S2     L34               ; (P) @|148| 
           B       .S2     L34               ; (P) @@|148| 

           SUB     .D2     B4,1,B0
||         MV      .D1     A7,A3
||         B       .S2     L34               ; (P) @@@|148| 

           SUB     .S1X    B4,1,A1
||         LDBU    .D1T1   *A3++,A4          ; (P) |147| 
|| [ B0]   SUB     .D2     B0,1,B0           ; (P) @@@@@|148| 
|| [ B0]   B       .S2     L34               ; (P) @@@@|148| 

;** --------------------------------------------------------------------------*
L34:    ; PIPED LOOP KERNEL

   [ B1]   SUB     .D2     B1,1,B1           ; 
|| [ A1]   SUB     .S1     A1,1,A1           ; 
|| [!B1]   ADD     .L1     A4,A0,A0          ; |147| 
|| [ A1]   LDBU    .D1T1   *A3++,A4          ; @@@@@|147| 
|| [ B0]   B       .S2     L34               ; @@@@@|148| 
|| [ B0]   SUB     .L2     B0,1,B0           ; @@@@@@|148| 

;** --------------------------------------------------------------------------*
L35:    ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
;** --------------------------------------------------------------------------*
L36:    
           B       .S2     B9                ; |155| 
           MVKL    .S1     0x1800004,A3      ; |151| 
           MVKH    .S1     0x1800004,A3      ; |151| 
           STW     .D1T1   A6,*A3            ; |151| 
           MV      .S1     A0,A4             ; |154| 
           NOP             1
           ; BRANCH OCCURS                   ; |155| 


;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES                                              *
;******************************************************************************
	.global	__BOARD_init