TMS320C6x COFF Assembler Version 4.10 Beta (May 4 2001) Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm PAGE 1
1 ;******************************************************************************
2 ;* TMS320C6x ANSI C Codegen Version 4.10 Beta (May 4 2001) *
3 ;* Date/Time created: Tue May 29 12:11:56 2001 *
4 ;******************************************************************************
5
6 ;******************************************************************************
7 ;* GLOBAL FILE PARAMETERS *
8 ;* *
9 ;* Architecture : TMS320C671x *
10 ;* Optimization : Enabled at level 3 *
11 ;* Optimizing for : Speed *
12 ;* Based on options: -o3, no -ms *
13 ;* Endian : Little *
14 ;* Interrupt Thrshld : Disabled *
15 ;* Memory Model : Large *
16 ;* Calls to RTS : Far *
17 ;* Pipelining : Enabled *
18 ;* Speculative Load : Disabled *
19 ;* Memory Aliases : Presume are aliases (pessimistic) *
20 ;* Debug Info : No Debug Info *
21 ;* *
22 ;******************************************************************************
23
24 .asg A15, FP
25 .asg B14, DP
26 .asg B15, SP
27 .global $bss
28
29
30 00000000 .sect ".cinit"
31 .align 8
32 00000000 00000004 .field 4,32
33 00000004 00000000- .field _initialized$1+0,32
34 00000008 00000000 .field 0,32 ; _initialized$1 @ 0
35 00000000 .sect ".text"
36 00000000 _initialized$1: .usect .far,4,4
37 ; c:\ti\c6000\cgtools\bin\opt6x.exe -qq -v6711 -O3 C:\WINDOWS\TEMP\TI506495_2 C:\WINDOWS\TEMP\TI
38 00000000 .sect ".text:__DIP_init"
39 .clink
40 .global __DIP_init
41
42 ;******************************************************************************
43 ;* FUNCTION NAME: __DIP_init *
44 ;* *
45 ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
46 ;* B5,B6,B7,B8,B9,SP *
47 ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
48 ;* B5,B6,B7,B8,B9,SP *
49 ;* Local Frame Size : 0 Args + 0 Auto + 12 Save = 12 byte *
50 ;******************************************************************************
51 00000000 __DIP_init:
52 ;** --------------------------------------------------------------------------*
53 00000000 00000028- MVKL .S1 _initialized$1,A0 ; |77|
54 00000004 00000068- MVKH .S1 _initialized$1,A0 ; |77|
55 00000008 00800264 LDW .D1T1 *A0,A1 ; |77|
TMS320C6x COFF Assembler Version 4.10 Beta (May 4 2001) Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm PAGE 2
56 0000000c 0200002A! MVKL .S2 __BOARD_init,B4 ; |78|
57 00000010 0200006A! MVKH .S2 __BOARD_init,B4 ; |78|
58 00000014 00002000 NOP 2
59 00000018 80000B10 [ A1] B .S1 L1 ; |77|
60 0000001c 05BC94F4 STW .D2T1 A11,*SP--(16) ; |74|
61
62 00000020 0180262B+ MVKL .S2 RL0,B3 ; |78|
63 00000024 01BC62F7 || STW .D2T2 B3,*+SP(12) ; |74|
64 00000028 058000A8 || MVK .S1 1,A11 ; |79|
65
66 0000002c 05000029- MVKL .S1 _initialized$1,A10 ; |79|
67 00000030 053C42F4 || STW .D2T1 A10,*+SP(8) ; |74|
68
69 00000034 05000069- MVKH .S1 _initialized$1,A10 ; |79|
70 00000038 81BC62E7 || [ A1] LDW .D2T2 *+SP(12),B3 ; |81|
71 0000003c 0180006A+ || MVKH .S2 RL0,B3 ; |78|
72
73 00000040 00000000 NOP 1
74 ; BRANCH OCCURS ; |77|
75 ;** --------------------------------------------------------------------------*
76 00000044 00100362 B .S2 B4 ; |78|
77 00000048 00008000 NOP 5
78 0000004c RL0: ; CALL OCCURS ; |78|
79 0000004c 05A80274 STW .D1T1 A11,*A10 ; |79|
80 00000050 01BC62E6 LDW .D2T2 *+SP(12),B3 ; |81|
81 00000054 00000000 NOP 1
82 ;** --------------------------------------------------------------------------*
83 00000058 L1:
84 00000058 053C42E4 LDW .D2T1 *+SP(8),A10 ; |81|
85 0000005c 05BC92E4 LDW .D2T1 *++SP(16),A11 ; |81|
86 00000060 00000000 NOP 1
87 00000064 000C0362 B .S2 B3 ; |81|
88 00000068 00008000 NOP 5
89 ; BRANCH OCCURS ; |81|
90
91
92 00000000 .sect ".text:_DIP_get"
93 .clink
94 .global _DIP_get
95
96 ;******************************************************************************
97 ;* FUNCTION NAME: _DIP_get *
98 ;* *
99 ;* Regs Modified : A0,A1,A3,A4,A5,A6,B0,B4,B5,B6,B7 *
100 ;* Regs Used : A0,A1,A3,A4,A5,A6,B0,B3,B4,B5,B6,B7 *
101 ;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
102 ;******************************************************************************
103 00000000 _DIP_get:
104 ;** --------------------------------------------------------------------------*
105 00000000 00000228 MVKL .S1 0x1800004,A0 ; |87|
106 00000004 0000C068 MVKH .S1 0x1800004,A0 ; |87|
107 00000008 02000266 LDW .D1T2 *A0,B4 ; |87|
108 0000000c 0280022A MVKL .S2 0x1800004,B5 ; |92|
109 00000010 0300022A MVKL .S2 0x1800004,B6 ; |93|
110 00000014 0280C06A MVKH .S2 0x1800004,B5 ; |92|
TMS320C6x COFF Assembler Version 4.10 Beta (May 4 2001) Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm PAGE 3
111 00000018 0300C06A MVKH .S2 0x1800004,B6 ; |93|
112 0000001c 039087CA CLR .S2 B4,4,7,B7 ; |92|
113 00000020 039CA58A SET .S2 B7,5,5,B7 ; |92|
114 00000024 039402F6 STW .D2T2 B7,*B5 ; |92|
115 00000028 029802E6 LDW .D2T2 *B6,B5 ; |93|
116 0000002c 01807828 MVK .S1 240,A3 ; |93|
117 00000030 00001028 MVK .S1 32,A0 ; |93|
118 00000034 03100058 MV .L1 A4,A6 ; |85|
119 00000038 02001028 MVK .S1 0x20,A4 ; |93|
120 0000003c 01947F78 AND .L1X A3,B5,A3 ; |93|
121 00000040 00806A78 CMPEQ .L1 A3,A0,A1 ; |93|
122 00000044 80000990 [ A1] B .S1 L5 ; |93|
123 00000048 02807828 MVK .S1 0xf0,A5 ; |93|
124 0000004c 800008C0 [ A1] ZERO .D1 A0 ; |96|
125 00000050 91800228 [!A1] MVKL .S1 0x1800004,A3 ; (P) |93|
126 00000054 9180C068 [!A1] MVKH .S1 0x1800004,A3 ; (P) |93|
127 00000058 900C0264 [!A1] LDW .D1T1 *A3,A0 ; (P) ^ |93|
128 ; BRANCH OCCURS ; |93|
129 ;** --------------------------------------------------------------------------*
130 0000005c 000000AA MVK .S2 0x1,B0
131 00000060 00004000 NOP 3
132 00000064 0180A7E0 AND .S1 A5,A0,A3 ; (P) ^ |93|
133 ;*----------------------------------------------------------------------------*
134 ;* SOFTWARE PIPELINE INFORMATION
135 ;*
136 ;* Loop source line : 93
137 ;* Loop opening brace source line : 0
138 ;* Loop closing brace source line : 0
139 ;* Known Minimum Trip Count : 1
140 ;* Known Max Trip Count Factor : 1
141 ;* Loop Carried Dependency Bound(^) : 8
142 ;* Unpartitioned Resource Bound : 2
143 ;* Partitioned Resource Bound(*) : 2
144 ;* Resource Partition:
145 ;* A-side B-side
146 ;* .L units 1 0
147 ;* .S units 2* 1
148 ;* .D units 1 0
149 ;* .M units 0 0
150 ;* .X cross paths 0 0
151 ;* .T address paths 1 0
152 ;* Long read paths 0 0
153 ;* Long write paths 0 0
154 ;* Logical ops (.LS) 1 0 (.L or .S unit)
155 ;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
156 ;* Bound(.L .S .LS) 2* 1
157 ;* Bound(.L .S .D .LS .LSD) 2* 1
158 ;*
159 ;* Searching for software pipeline schedule at ...
160 ;* ii = 8 Schedule found with 2 iterations in parallel
161 ;* done
162 ;*
163 ;* Loop is interruptible
164 ;* Collapsed epilog stages : 1
165 ;* Prolog not removed
TMS320C6x COFF Assembler Version 4.10 Beta (May 4 2001) Tue May 29 12:11:56 2001
Copyright (c) 1996-2001 Texas Instruments Incorporated
bsl_dip.asm PAGE 4
166 ;* Collapsed prolog stages : 0
167 ;*
168 ;* Minimum required memory pad : 0 bytes
169 ;*
170 ;* Minimum safe trip count : 1
171 ;*----------------------------------------------------------------------------*
172 00000068 L2: ; PIPED LOOP PROLOG
173 ;** --------------------------------------------------------------------------*
174 00000068 L3: ; PIPED LOOP KERNEL
175
176 00000068 00906A79 CMPEQ .L1 A3,A4,A1 ; ^ |93|
177 0000006c 01800228 || MVKL .S1 0x1800004,A3 ; @|93|
178
179 00000070 800428C3 [ A1] ZERO .D2 B0 ; ^
180 00000074 0180C068 || MVKH .S1 0x1800004,A3 ; @|93|
181
182 00000078 20000113 [ B0] B .S2 L3 ; |93|
183 0000007c 200C0264 || [ B0] LDW .D1T1 *A3,A0 ; @ ^ |93|
184
185 00000080 00006000 NOP 4
186 00000084 0180A7E0 AND .S1 A5,A0,A3 ; @ ^ |93|
187 ;** --------------------------------------------------------------------------*
188 00000088 L4: ; PIPED LOOP EPILOG
189 ;** --------------------------------------------------------------------------*
190 00000088 000008C0 ZERO .D1 A0 ; |96|
191 ;** --------------------------------------------------------------------------*
192 0000008c L5:
193 0000008c 00480468 MVKH .S1 0x90080000,A0 ; |96|
194 00000090 00800264 LDW .D1T1 *A0,A1 ; |96|
195 00000094 0280022A MVKL .S2 0x1800004,B5 ; |100|
196 00000098 0280C06A MVKH .S2 0x1800004,B5 ; |100|
197 0000009c 000C0362 B .S2 B3 ; |103|
198 000000a0 021402F6 STW .D2T2 B4,*B5 ; |100|
199 000000a4 000709A0 SHRU .S1 A1,24,A0 ; |97|
200 000000a8 0080C7E0 AND .S1 A6,A0,A1 ; |97|
201 000000ac 808000A8 [ A1] MVK .S1 0x1,A1 ; |98|
202 000000b0 02040940 MV .D1 A1,A4 ; |102|
203 ; BRANCH OCCURS ; |103|
204
205
206 ;******************************************************************************
207 ;* UNDEFINED EXTERNAL REFERENCES *
208 ;******************************************************************************
209 .global __BOARD_init
No Assembly Errors, No Assembly Warnings