TMS320C6xxx Software Debugger/Emulator Emulator Revision 2.05.01 - January 1999 Note: The terms debugger and emulator are used interchangeably in this document. ========================================================================== Table of Contents: ================== 1. Software Debugger/Emulator Version 2.05.01 Errata 2. Software Debugger/Emulator Version 2.05.01 Notes 1. Software Debugger/Emulator Version 2.05.01 Errata ===================================================== - IER Bit 0 (Reset Interrupt Enable bit). Bit 0 of the Interrupt Enable Register displays incorrectly in the debugger window. Although this bit always displays as '0' on the debugger, it is actually always '1' (it is tied high on chip). 2. Software Debugger/Emulator Version 2.05.01 Notes =================================================== - Software Reset The DSP reset command from the Code Composer Debug menu will do a full chip reset on c6x chip revisions 2.0 and newer. If in boot mode, a software reset will initiate a boot load. - Boot Loading Do not invoke the emulator while boot loading is in progress. This mainly affects HPI boot where the host has to explicitly end the boot process. For HPI boot load to finish, the host must send a DSPINT signal to the c6x through the HPI, in order for the user to bring up the emulator reliably. For non HPI boot modes, a conscious effort is not needed to avoid this problem, since boot loading will typically complete within one second after reset. - Hardware Breakpoints Hardware breakpoints cannot be set or cleared on instructions that are within in the instruction pipeline. - PC Register The PC displayed in the CPU window is the E1 pipeline phase PC. This PC points to the start of the next execute packet. Steps are performed on pipeline cycle boundaries. - Emulation Memory View The C6xxx Emulator provides visibility to the register file on pipeline cycle boundaries. While halting, ST instructions that are already past E1 pipeline phase are completed providing a memory view that reflects what the next LD instruction will read from memory. Also while halting, LD instructions that are already in the pipeline are completed, but the data read is saved by the emulator and restored into the pipeline when execution is resumed. - Memory Mapping [does not apply to 2.05.01 release] The C6xxx Emulator can only distinguish between program and data bus memory through the memory map. The Emulator will generate program bus accesses for memory mapped as PRAM or PROM. If the map is off, only memory linked to the .text section will be downloaded over the program bus. All data memory accesses are made through the B-side data bus. If the emulator is requested to access an illegal or reserved memory location, an error is posted in the EMIF control register and zero is returned as the data. Do not map the cache memory area in the emulator. Manual display of a cache memory location can cause the emulator to crash. - Program Memory Memory reads of 8- or 16-bit values from program memory, results in the emulator displaying 0. Program memory writes of 8- or 16-bit values results in no value being written to memory. - Software Breakpoint Rule The emulator will only allow one software breakpoint per execute packet to be set. This rule is enforced by the emulator. Software breakpoints may be set and cleared on instructions that are within the instruction pipeline. - CPU/Chip-Level Peripherals Synchronization When the emulator halts it also halts all the internal memory controllers. This is required since the memory controller's pipeline must remain synchronized to the processor's pipeline. - Ready The emulator will timeout if the memory system's ready signal is not driven active within 0.1 seconds of a memory access. - Single Step Limitations The pipeline architecture does not allow the emulator to step into an interrupt using the RUN 1 command. To halt on the first location of a ISR the user must set a software breakpoint or a program address breakpoint on the first instruction of the ISR and perform a RUN 0 command. - Code Downloads The emulator utilizes a new code download mechanism. If your memory system cannot access memory within 32 TCLKs (if you are using the TI provided clock this will be 3.2 Usecs) then the emulator will switch and utilize a slower mechanism. - Reset The emulator can be initialized while reset is held low. If reset is driven high while the emulator has the processor halted, the processor can be single stepped by the emulator to the reset vector. - EMU0/1 Output Trigger EMU0/1 will not trigger out if the processor is halted during the pipe-up (within five execute packets of the current PC) or during single-stepping. - EMU Pins' Pull-ups The EMU pins must be pulled up during execution of emurst. Emurst will pull TRST active, which will cause the C6xxx's CPU JTAG port to be selected. - Debugger start-up. If the processor is in an error state (as a result of executing invalid code,etc.) when the emulator is invoked, the emulator software will try to perform a software reset and bring up the device in reset mode. If a reset is performed by the emulator, the message, "Processor initialized to reset state" will be displayed in the emulator window and the reset pending bit will be set in the IFR. To clear the reset pending bit in the IFR, you can do the following: 1) Perform a reset command from the debugger window. This will do a software reset and clear the pending reset bit. OR 2) Run your code, but bear in mind it will run from the reset vector address location 0x0. END OF README