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Release 5.2.03i - Trace F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -quiet -e 3 -l 3 -xml count4 count4.ncd -o count4.twr
count4.pcf

Design file:              count4.ncd
Physical constraint file: count4.pcf
Device,speed:             xc2s200e,-7 (PRODUCTION 1.17 2003-05-08)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Q<0>        |    8.900(R)|clk_BUFGP         |   0.000|
Q<1>        |    8.926(R)|clk_BUFGP         |   0.000|
Q<2>        |    9.169(R)|clk_BUFGP         |   0.000|
Q<3>        |    9.255(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    5.099|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Sep 30 14:38:26 2003
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