Release 5.2.03i - xst F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.61 s | Elapsed : 0.00 / 0.00 s --> Reading design: count4.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Low Level Synthesis 6) Final Report 6.1) Device utilization summary 6.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : count4.prj Input Format : VERILOG Ignore Synthesis Constraint File : NO Verilog Search Path : Verilog Include Directory : ---- Target Parameters Output File Name : count4 Output Format : NGC Target Device : xc2s200e-7pq208 ---- Source Options Top Module Name : count4 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Complex Clock Enable Extraction : YES Multiplier Style : lut Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 100 Add Generic Clock Buffer(BUFG) : 4 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Criterion : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Top module area constraint : 100 Top module allowed area overflow : 5 ---- Other Options read_cores : YES cross_clock_analysis : NO verilog2001 : YES ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "count4.prj" Compiling include file "../../count4.v" Module compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v" No errors in compilation ========================================================================= * HDL Analysis * ========================================================================= Analysis of file succeeded. Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is ../../count4.v. Found 30-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 1 30-bit up counter : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Library "C:/Xilinx/data/librtl.xst" Consulted Optimizing unit ... Mapping all equations... Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx. Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block count4, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : count4.ngr Top Level Output File Name : count4 Output Format : NGC Optimization Criterion : Speed Keep Hierarchy : NO Macro Generator : macro+ Design Statistics # IOs : 6 Macro Statistics : # Registers : 1 # 30-bit register : 1 # Adders/Subtractors : 1 # 30-bit adder : 1 Cell Usage : # BELS : 90 # GND : 1 # LUT1 : 1 # LUT1_D : 1 # LUT1_L : 28 # MUXCY : 29 # VCC : 1 # XORCY : 29 # FlipFlops/Latches : 30 # FDC : 30 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 5 # IBUF : 1 # OBUF : 4 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s200epq208-7 Number of Slices: 17 out of 2352 0% Number of Slice Flip Flops: 30 out of 4704 0% Number of 4 input LUTs: 30 out of 4704 0% Number of bonded IOBs: 5 out of 146 3% Number of GCLKs: 1 out of 4 25% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 30 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -7 Minimum period: 5.276ns (Maximum Frequency: 189.537MHz) Minimum input arrival time before clock: 3.949ns Maximum output required time after clock: 6.277ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 5.276ns (Levels of Logic = 31) Source: T_0 Destination: T_29 Source Clock: clk rising Destination Clock: clk rising Data Path: T_0 to T_29 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 1 0.886 0.828 T_0 (T_0) LUT1_D:I0->LO 1 0.418 0.000 T_Madd__n0000_inst_lut2_01 (N632) MUXCY:S->O 1 0.461 0.000 T_Madd__n0000_inst_cy_0 (T_Madd__n0000_inst_cy_0) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_1 (T_Madd__n0000_inst_cy_1) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_2 (T_Madd__n0000_inst_cy_2) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_3 (T_Madd__n0000_inst_cy_3) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_4 (T_Madd__n0000_inst_cy_4) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_5 (T_Madd__n0000_inst_cy_5) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_6 (T_Madd__n0000_inst_cy_6) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_7 (T_Madd__n0000_inst_cy_7) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_8 (T_Madd__n0000_inst_cy_8) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_9 (T_Madd__n0000_inst_cy_9) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_10 (T_Madd__n0000_inst_cy_10) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_11 (T_Madd__n0000_inst_cy_11) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_12 (T_Madd__n0000_inst_cy_12) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_13 (T_Madd__n0000_inst_cy_13) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_14 (T_Madd__n0000_inst_cy_14) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_15 (T_Madd__n0000_inst_cy_15) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_16 (T_Madd__n0000_inst_cy_16) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_17 (T_Madd__n0000_inst_cy_17) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_18 (T_Madd__n0000_inst_cy_18) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_19 (T_Madd__n0000_inst_cy_19) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_20 (T_Madd__n0000_inst_cy_20) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_21 (T_Madd__n0000_inst_cy_21) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_22 (T_Madd__n0000_inst_cy_22) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_23 (T_Madd__n0000_inst_cy_23) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_24 (T_Madd__n0000_inst_cy_24) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_25 (T_Madd__n0000_inst_cy_25) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_26 (T_Madd__n0000_inst_cy_26) MUXCY:CI->O 1 0.052 0.000 T_Madd__n0000_inst_cy_27 (T_Madd__n0000_inst_cy_27) MUXCY:CI->O 0 0.052 0.000 T_Madd__n0000_inst_cy_28 (T_Madd__n0000_inst_cy_28) XORCY:CI->O 1 0.579 0.000 T_Madd__n0000_inst_sum_29 (T__n0000<29>) FDC:D 0.648 T_29 ---------------------------------------- Total 5.276ns (4.448ns logic, 0.828ns route) (84.3% logic, 15.7% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 3.949ns (Levels of Logic = 1) Source: R Destination: T_28 Destination Clock: clk rising Data Path: R to T_28 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 30 0.769 2.664 R_IBUF (R_IBUF) FDC:CLR 0.516 T_28 ---------------------------------------- Total 3.949ns (1.285ns logic, 2.664ns route) (32.5% logic, 67.5% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 6.277ns (Levels of Logic = 1) Source: T_28 Destination: Q<2> Source Clock: clk rising Data Path: T_28 to Q<2> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 2 0.886 0.965 T_28 (T_28) OBUF:I->O 4.426 Q_2_OBUF (Q<2>) ---------------------------------------- Total 6.277ns (5.312ns logic, 0.965ns route) (84.6% logic, 15.4% route) ========================================================================= CPU : 3.85 / 4.89 s | Elapsed : 4.00 / 5.00 s --> Total memory usage is 66272 kilobytes