Release 5.2.03i - Par F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. B200-15:: Tue Sep 30 14:38:18 2003 C:/Xilinx/bin/nt/par.exe -w -ol 2 -t 1 count4_map.ncd count4.ncd count4.pcf Constraints file: count4.pcf Loading device database for application par from file "count4_map.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application par from file '2s200e.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.17 2003-05-08. Resolved that GCLKIOB must be placed at site P80. Resolved that IOB > must be placed at site P44. Resolved that IOB > must be placed at site P46. Resolved that IOB > must be placed at site P48. Resolved that IOB > must be placed at site P55. Resolved that IOB must be placed at site P40. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 5 out of 142 3% Number of LOCed External IOBs 5 out of 5 100% Number of SLICEs 15 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Phase 1.1 Phase 1.1 (Checksum:98969f) REAL time: 3 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs Phase 3.8 ........ Phase 3.8 (Checksum:98b650) REAL time: 3 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 3 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs Writing design to file count4.ncd. Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 2 secs Starting Router REAL time: 3 secs Phase 1: 81 unrouted; REAL time: 3 secs Phase 2: 66 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 4 secs Finished Router REAL time: 4 secs Total REAL time to router completion: 4 secs Total CPU time to router completion: 3 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 15 | 0.017 | 0.406 | +----------------------------+----------+--------+------------+-------------+ The Delay Summary Report The Score for this design is: 80 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 0.593 ns The Maximum Pin Delay is: 2.407 ns The Average Connection Delay on the 10 Worst Nets is: 1.077 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 64 13 4 0 0 0 All signals are completely routed. Total REAL time to par completion: 4 secs Total CPU time to par completion: 3 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file count4.ncd. PAR done.