Release 5.2.03i - Map F.31 Xilinx Mapping Report File for Design 'count4' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -quiet -p xc2s200e-pq208-7 -cm area -pr b -k 4 -c 100 -tx off -o count4_map.ncd count4.ngd count4.pcf Target Device : x2s200e Target Package : pq208 Target Speed : -7 Mapper Version : spartan2e -- $Revision: 1.4 $ Mapped Date : Tue Sep 30 14:38:15 2003 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 30 out of 4,704 1% Number of 4 input LUTs: 1 out of 4,704 1% Logic Distribution: Number of occupied Slices: 15 out of 2,352 1% Number of Slices containing only related logic: 15 out of 15 100% Number of Slices containing unrelated logic: 0 out of 15 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 16 out of 4,704 1% Number used as logic: 1 Number used as a route-thru: 15 Number of bonded IOBs: 5 out of 142 3% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 420 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 56 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:LIT:95 - All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | clk | GCLKIOB | INPUT | LVTTL | | | | | | | Q<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Q<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Q<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Q<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | R | IOB | INPUT | LVTTL | | | | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design. Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design.