Project Navigator Auto-Make Log File ------------------------------------- JHDPARSE - VHDL/Verilog Parser. ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v Scanning c:\tested\count4.v Writing count4.jhd. JHDPARSE complete - 0 errors, 0 warnings. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "count4.prj" Compiling include file "../../count4.v" Module compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v" No errors in compilation ========================================================================= * HDL Analysis * ========================================================================= Analysis of file succeeded. Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is ../../count4.v. Found 4-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 1 4-bit up counter : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Library "C:/Xilinx/data/librtl.xst" Consulted Optimizing unit ... Mapping all equations... Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx. Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block count4, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s200epq208-7 Number of Slices: 3 out of 2352 0% Number of Slice Flip Flops: 4 out of 4704 0% Number of 4 input LUTs: 4 out of 4704 0% Number of bonded IOBs: 5 out of 146 3% Number of GCLKs: 1 out of 4 25% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -7 Minimum period: 4.061ns (Maximum Frequency: 246.245MHz) Minimum input arrival time before clock: 2.437ns Maximum output required time after clock: 6.277ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -quiet -dd c:\tested\test\count/_ngo -i -p xc2s200e-pq208-7 count4.ngc count4.ngd Reading NGO file "C:/testED/test/count/count4.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "count4.ngd" ... Writing NGDBUILD log file "count4.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "2s200epq208-7". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 4,704 1% Number of 4 input LUTs: 1 out of 4,704 1% Logic Distribution: Number of occupied Slices: 2 out of 2,352 1% Number of Slices containing only related logic: 2 out of 2 100% Number of Slices containing unrelated logic: 0 out of 2 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 3 out of 4,704 1% Number used as logic: 1 Number used as a route-thru: 2 Number of bonded IOBs: 5 out of 142 3% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 56 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 55 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "count4_map.mrp" for details. Completed process "Map". Mapping Module count4 . . . MAP command line: map -quiet -p xc2s200e-pq208-7 -cm area -pr b -k 4 -c 100 -tx off -o count4_map.ncd count4.ngd count4.pcf Mapping Module count4: DONE Started process "Place & Route". Release 5.2.03i - Par F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Constraints file: count4.pcf Loading device database for application par from file "count4_map.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application par from file '2s200e.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.17 2003-05-08. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 5 out of 142 3% Number of LOCed External IOBs 0 out of 5 0% Number of SLICEs 2 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Phase 1.1 Phase 1.1 (Checksum:98969f) REAL time: 2 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.8 . Phase 5.8 (Checksum:989fdf) REAL time: 3 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 3 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs Writing design to file count4.ncd. Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 2 secs Starting Router REAL time: 3 secs Phase 1: 16 unrouted; REAL time: 3 secs Phase 2: 14 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 3 secs Finished Router REAL time: 3 secs Total REAL time to router completion: 3 secs Total CPU time to router completion: 3 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 2 | 0.000 | 0.402 | +----------------------------+----------+--------+------------+-------------+ All signals are completely routed. Total REAL time to par completion: 4 secs Total CPU time to par completion: 3 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file count4.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Loading device database for application trce.exe from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application trce.exe from file '2s200e.nph' in environment C:/Xilinx. Analysis completed Tue Sep 30 14:26:51 2003 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module count4 . . . PAR command line: par -w -ol 2 -t 1 count4_map.ncd count4.ncd count4.pcf PAR completed successfully Project Navigator Auto-Make Log File ------------------------------------- Started process "View Locked Pin Constraints". pin2ucf: Xilinx Pin Locker F.28.Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Loading device database for application pin2ucf from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application pin2ucf from file '2s200e.nph' in environment C:/Xilinx. Pin Locking constraints file generated in : count4_locked.ucf Completed process "View Locked Pin Constraints". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -quiet -dd c:\tested\test\count/_ngo -uc ../../count4.ucf -p xc2s200e-pq208-7 count4.ngc count4.ngd Reading NGO file "C:/testED/test/count/count4.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "../../count4.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "count4.ngd" ... Writing NGDBUILD log file "count4.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "2s200epq208-7". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 4,704 1% Number of 4 input LUTs: 1 out of 4,704 1% Logic Distribution: Number of occupied Slices: 2 out of 2,352 1% Number of Slices containing only related logic: 2 out of 2 100% Number of Slices containing unrelated logic: 0 out of 2 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 3 out of 4,704 1% Number used as logic: 1 Number used as a route-thru: 2 Number of bonded IOBs: 5 out of 142 3% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 56 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 55 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "count4_map.mrp" for details. Completed process "Map". Mapping Module count4 . . . MAP command line: map -quiet -p xc2s200e-pq208-7 -cm area -pr b -k 4 -c 100 -tx off -o count4_map.ncd count4.ngd count4.pcf Mapping Module count4: DONE Started process "Place & Route". Release 5.2.03i - Par F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Constraints file: count4.pcf Loading device database for application par from file "count4_map.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application par from file '2s200e.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.17 2003-05-08. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 5 out of 142 3% Number of LOCed External IOBs 5 out of 5 100% Number of SLICEs 2 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Phase 1.1 Phase 1.1 (Checksum:98969f) REAL time: 2 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs Phase 3.8 . Phase 3.8 (Checksum:98a327) REAL time: 2 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs Writing design to file count4.ncd. Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 2 secs Starting Router REAL time: 3 secs Phase 1: 16 unrouted; REAL time: 3 secs Phase 2: 14 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 3 secs Finished Router REAL time: 3 secs Total REAL time to router completion: 3 secs Total CPU time to router completion: 3 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 2 | 0.007 | 0.406 | +----------------------------+----------+--------+------------+-------------+ All signals are completely routed. Total REAL time to par completion: 4 secs Total CPU time to par completion: 3 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file count4.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Loading device database for application trce.exe from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application trce.exe from file '2s200e.nph' in environment C:/Xilinx. Analysis completed Tue Sep 30 14:31:43 2003 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module count4 . . . PAR command line: par -w -ol 2 -t 1 count4_map.ncd count4.ncd count4.pcf PAR completed successfully Started process "Generate Programming File". Release 5.2.03i - Bitgen F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application Bitgen from file '2s200e.nph' in environment C:/Xilinx. Opened constraints file count4.pcf. Tue Sep 30 14:31:46 2003 Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "count4.bit". Bitstream generation is complete. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- JHDPARSE - VHDL/Verilog Parser. ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v Scanning c:\tested\count4.v Writing count4.jhd. JHDPARSE complete - 0 errors, 0 warnings. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "count4.prj" Compiling include file "../../count4.v" Module compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v" No errors in compilation ========================================================================= * HDL Analysis * ========================================================================= Analysis of file succeeded. Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is ../../count4.v. Found 20-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 1 20-bit up counter : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Library "C:/Xilinx/data/librtl.xst" Consulted Optimizing unit ... Mapping all equations... Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx. Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block count4, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s200epq208-7 Number of Slices: 11 out of 2352 0% Number of Slice Flip Flops: 20 out of 4704 0% Number of 4 input LUTs: 20 out of 4704 0% Number of bonded IOBs: 5 out of 146 3% Number of GCLKs: 1 out of 4 25% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 20 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -7 Minimum period: 4.756ns (Maximum Frequency: 210.261MHz) Minimum input arrival time before clock: 3.589ns Maximum output required time after clock: 6.277ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -quiet -dd c:\tested\test\count/_ngo -uc ../../count4.ucf -p xc2s200e-pq208-7 count4.ngc count4.ngd Reading NGO file "C:/testED/test/count/count4.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "../../count4.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "count4.ngd" ... Writing NGDBUILD log file "count4.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "2s200epq208-7". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 20 out of 4,704 1% Number of 4 input LUTs: 1 out of 4,704 1% Logic Distribution: Number of occupied Slices: 10 out of 2,352 1% Number of Slices containing only related logic: 10 out of 10 100% Number of Slices containing unrelated logic: 0 out of 10 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 11 out of 4,704 1% Number used as logic: 1 Number used as a route-thru: 10 Number of bonded IOBs: 5 out of 142 3% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 280 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 56 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "count4_map.mrp" for details. Completed process "Map". Mapping Module count4 . . . MAP command line: map -quiet -p xc2s200e-pq208-7 -cm area -pr b -k 4 -c 100 -tx off -o count4_map.ncd count4.ngd count4.pcf Mapping Module count4: DONE Started process "Place & Route". Release 5.2.03i - Par F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Constraints file: count4.pcf Loading device database for application par from file "count4_map.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application par from file '2s200e.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.17 2003-05-08. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 5 out of 142 3% Number of LOCed External IOBs 5 out of 5 100% Number of SLICEs 10 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Phase 1.1 Phase 1.1 (Checksum:98969f) REAL time: 3 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs Phase 3.8 ........ Phase 3.8 (Checksum:98aca5) REAL time: 3 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 3 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs Writing design to file count4.ncd. Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 2 secs Starting Router REAL time: 3 secs Phase 1: 56 unrouted; REAL time: 3 secs Phase 2: 46 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 3 secs Finished Router REAL time: 3 secs Total REAL time to router completion: 4 secs Total CPU time to router completion: 3 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 10 | 0.017 | 0.406 | +----------------------------+----------+--------+------------+-------------+ All signals are completely routed. Total REAL time to par completion: 4 secs Total CPU time to par completion: 3 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file count4.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Loading device database for application trce.exe from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application trce.exe from file '2s200e.nph' in environment C:/Xilinx. Analysis completed Tue Sep 30 14:35:46 2003 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module count4 . . . PAR command line: par -w -ol 2 -t 1 count4_map.ncd count4.ncd count4.pcf PAR completed successfully Started process "Generate Programming File". Release 5.2.03i - Bitgen F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application Bitgen from file '2s200e.nph' in environment C:/Xilinx. Opened constraints file count4.pcf. Tue Sep 30 14:35:49 2003 Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "count4.bit". Bitstream generation is complete. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- JHDPARSE - VHDL/Verilog Parser. ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Scanning C:/Xilinx/verilog/src/iSE/unisim_comp.v Scanning c:\tested\count4.v Writing count4.jhd. JHDPARSE complete - 0 errors, 0 warnings. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "count4.prj" Compiling include file "../../count4.v" Module compiled Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v" No errors in compilation ========================================================================= * HDL Analysis * ========================================================================= Analysis of file succeeded. Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is ../../count4.v. Found 30-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 1 30-bit up counter : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Library "C:/Xilinx/data/librtl.xst" Consulted Optimizing unit ... Mapping all equations... Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx. Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block count4, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s200epq208-7 Number of Slices: 17 out of 2352 0% Number of Slice Flip Flops: 30 out of 4704 0% Number of 4 input LUTs: 30 out of 4704 0% Number of bonded IOBs: 5 out of 146 3% Number of GCLKs: 1 out of 4 25% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 30 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -7 Minimum period: 5.276ns (Maximum Frequency: 189.537MHz) Minimum input arrival time before clock: 3.949ns Maximum output required time after clock: 6.277ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -quiet -dd c:\tested\test\count/_ngo -uc ../../count4.ucf -p xc2s200e-pq208-7 count4.ngc count4.ngd Reading NGO file "C:/testED/test/count/count4.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "../../count4.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "count4.ngd" ... Writing NGDBUILD log file "count4.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "2s200epq208-7". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 30 out of 4,704 1% Number of 4 input LUTs: 1 out of 4,704 1% Logic Distribution: Number of occupied Slices: 15 out of 2,352 1% Number of Slices containing only related logic: 15 out of 15 100% Number of Slices containing unrelated logic: 0 out of 15 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 16 out of 4,704 1% Number used as logic: 1 Number used as a route-thru: 15 Number of bonded IOBs: 5 out of 142 3% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 420 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 56 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "count4_map.mrp" for details. Completed process "Map". Mapping Module count4 . . . MAP command line: map -quiet -p xc2s200e-pq208-7 -cm area -pr b -k 4 -c 100 -tx off -o count4_map.ncd count4.ngd count4.pcf Mapping Module count4: DONE Started process "Place & Route". Release 5.2.03i - Par F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Constraints file: count4.pcf Loading device database for application par from file "count4_map.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application par from file '2s200e.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.17 2003-05-08. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 5 out of 142 3% Number of LOCed External IOBs 5 out of 5 100% Number of SLICEs 15 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) Phase 1.1 Phase 1.1 (Checksum:98969f) REAL time: 3 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs Phase 3.8 ........ Phase 3.8 (Checksum:98b650) REAL time: 3 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 3 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs Writing design to file count4.ncd. Total REAL time to placer completion: 3 secs Total CPU time to placer completion: 2 secs Starting Router REAL time: 3 secs Phase 1: 81 unrouted; REAL time: 3 secs Phase 2: 66 unrouted; REAL time: 3 secs Phase 3: 0 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 4 secs Finished Router REAL time: 4 secs Total REAL time to router completion: 4 secs Total CPU time to router completion: 3 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 15 | 0.017 | 0.406 | +----------------------------+----------+--------+------------+-------------+ All signals are completely routed. Total REAL time to par completion: 4 secs Total CPU time to par completion: 3 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file count4.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Loading device database for application trce.exe from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application trce.exe from file '2s200e.nph' in environment C:/Xilinx. Analysis completed Tue Sep 30 14:38:26 2003 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module count4 . . . PAR command line: par -w -ol 2 -t 1 count4_map.ncd count4.ncd count4.pcf PAR completed successfully Started process "Generate Programming File". Release 5.2.03i - Bitgen F.31 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "count4.ncd". "count4" is an NCD, version 2.37, device xc2s200e, package pq208, speed -7 Loading device for application Bitgen from file '2s200e.nph' in environment C:/Xilinx. Opened constraints file count4.pcf. Tue Sep 30 14:38:29 2003 Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "count4.bit". Bitstream generation is complete. Completed process "Generate Programming File".