module slowclock(clock, reset, slowclock);
input clock, reset;
output slowclock;
reg slowclock;
reg [13:0] clockdiv;    //this register sized  for a big value for parameter maxcount
// For simulation only,cut clock frequency by a factor of 1, 2, 3, 4.....
parameter maxcount = 3;

//Clock divider 
 always  @  (posedge clock or posedge reset)
	if (reset) begin
	   clockdiv <= 0;
	    slowclock <= 0;
	end
	else if (clockdiv==maxcount) begin
	   slowclock <=1;
	  clockdiv <=0;
	  end
	else  begin 
	  slowclock <= 0;
                    clockdiv <= clockdiv+1;
                  end
endmodule