module classexample_TB;
reg clk;
reg reset;
reg R, S, T, W;
wire Y;

 classexample DUT (
.clk(clk),
.reset(reset),
.R(R),
.S(S),
.T(T),
.W(W), 
.Y(Y)
);

 initial
 begin

clk=0;
reset=1;
 R=1;  S=0; T=1; W=0;
#5 reset=0;
 R=1;  S=0; T=0; W=0;
#5
 R=1;  S=0; T=0; W=1;

#100
 $finish;
end

always #10  clk=~clk;

endmodule