module classexample (clk, reset,  R, S, T, W, Y);
 input clk, reset;
input R, S, T, W;
 output Y;
  reg Y;
 reg [1:0] Q;
   

always@(R or S or T or W or Q)
 case (Q)
 2'b00: Y=R;
 2'b01 : Y=S;
 2'b10: Y=T;
 2'b11: Y=W;
default: Y=1'b0;
endcase

always@ (posedge clk or posedge reset)
if (reset==1)
Q<=0;
else
 Q<=Q+1;

endmodule