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Course ECE 330 


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Class time and place :

T,Th/9:55-10:45 a.m./Crapo Hall G313 (section 1)

T, Th/ 1:35-2:25p.m. /Crapo Hall G313 (section 2)

Lab time and room:  

We,Fr/ 8:05-10:45 a.m./C115, Moench Hall (section1)

 We,Fr/1:35-4:15 a.m. /C115, Moench Hall (section 2)

Office Hours:      

T, Th/ 4:20-5: 10 and We, Fr/ 10: 50-11:40 (or just stop by)

Office location:         MOENCH  HALL/F204



 Required textbook: Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, McGraw-Hill Companies, Inc., 2003.

Lab Book:  Bill Eccles “ECE 330- Digital Design Laboratory”(to be distributed in class)

Recommended text book:

John F. Wakerly “Digital Design Principles and Practices” 3rd Edition Updated, , Prentice-Hall, 2001 (electrical charactheristics of  CMOS and TTL logic circuits, ABEL )

Thomas Floyd “Digital Fundamentals”, 8 th  edition, 2003 ( PLDs, ABEL)

Michael D. Ciletti “Advanced Digital Design with the Verilog HDL”, Pearson Education, Inc., Upper Saddle River, New Jersey 07458, 2003.




Course objectives: This is the second course in digital design after ECE130, where principles of digital system design are covered. This course will introduce a number a number of practical issues in digital system design such as device electrical characteristics, I/O behavior, modeling and device interfacing. It will also introduce hardware description languages (ABEL, Verilog) to describe a digital design and discuss design and implementation of combinational and sequential circuits with programmable logic devices such as Gate Array Logic chips (GAL) and  Field Programmable Gate Array chips (FPGA).


 Laboratory:  Labs are performed in groups of two students. One lab notebook should be maintained within each group. If is required, a prelab  will be due before the lab period and will account for 10% to 40% of the final lab grade. A late demonstration and a regular lab report will carry a 10 % grade reduction for each day it is late.

Lab formal reports:  Labs 6, 7, 8, 9 will require a formal lab report on completed projects. Each formal lab report   will be written by one student from a lab group. Only the author of the report will get credit.  Authorship will alternate from one team member to another through labs  6, 7, 8, 9.

 Grading Policy: Because this course does not have a final exam, the  final grade has the following distribution;

Lab 1b


Lab 3b


Lab 5 b


Lab7 report


Lab 9 report


Lab 2a


Lab 4a


Lab 6


Lab 8




Lab 2b


Lab 4b


Lab 6 report

8 %

Lab 8





Lab 3a


Lab 5a


Lab 7






 The cumulative score must be at a passing level (i.e>= 60%) in order to pass the course. All lab works (prelabs, lab  reports) must be submitted in order to pass the course.


ECE Department  course objectives:

 After successfully completing this course the student should be able to:

1. Have an improved understanding of combinational and sequential logic design initially encountered in EC 130.

2. Design, implement in hardware and test various logical systems, both combinational and sequential.

3. Understand at a basic level the differences among TTL, PLA/GAL, and FPGA devices by developing circuits using each family.

4. Describe logical systems in a high-level language such as VHDL or Verilog.

5. Manipulate an industrial-strength design automation tool such as the Xilinx Foundation Series.

6. Continue the practice of working in pairs to reach a common goal.

7. Prepare formal reports on completed projects.

8. Use external resources and self-learning to learn to use tools and devices.



Last modified: Thursday April 29, 2004