Single-Chip Exponential Calculator

 

Introduction

Last week you performed a gate-level design on a moderately complex combinational circuit. This week you will implement the same design using a programmable logic device, or PLD. You will work with a variety of PLDs of varying complexity in this course, so your first introduction to these devices will be to a simple PLD called generic array logic, or GAL.

Objectives

bulletLearn how to implement a Verilog-based design in a GAL (generic array logic)
bulletDesign, implement, and test a combinational logic circuit using a single GAL chip

Parts List

bulletGAL22V10 PLD
bulletConductive foam for GAL device (always carry the chip in the conductive foam to avoid damage from electrostatic discharge, or ESD)
bullet74HC4040 12-stage binary counter

Equipment

bulletAgilent 54622D mixed-signal oscilloscope (MSO)
bulletDigital probes for MSO
bulletAgilent 33120A function/arbitrary waveform generator
bulletFixed 5-volt power supply
bulletBreadboard
bulletFloppy Disk

Software

bulletCadence NC-Simulator: Verilog behavioral simulator (download from Tibia)
bulletLattice ispLEVER: used to convert the design files (on lab machines)

Prelab

  1. Familiarize yourself with the basic architecture of the GAL PLD by studying the datasheet for the Lattice Semiconductor GAL22V10.
     
  2. Read Design Flow: GAL, Verilog to learn how to use Lattice Semiconductor's ispLEVER software to program a GAL from a Verilog source file.
     
  3. Download the Cadence NC-Simulator from Tibia. Follow the NC-Simulator Download Instructions to install the software on your machine.
     
  4. Create a Verilog description for half of a NAND gate (the so-called "half-gate" circuit, or inverter). Verify your design using a testbench circuit. Include a hardcopy of both the .v and the testbench files and the waveforms from your simulation.
     
  5. Write a Verilog description for the Exponential Calculator that was specified in Lab 1. Implement all four output bits. Attach your final hardcopy to a lab book page.
     
  6. Develop a testbench circuit to simulate and verify your design using the Cadence NC Simulator. Attach hardcopy of your testbench file and your waveforms to a lab book page. Summarize how you know that the simulation results tell you that the your design works correctly.

    NOTE: Do not proceed to hardware implementation until your simulation is 100% correct!
     
  7. A photocopy of your prelab pages is due at the beginning of lab.

Lab

  1. As a warm-up, implement a single inverter (a "half gate") in a GAL. Apply a squarewave source to the input, and confirm that you observe the inverted signal on the output.

    NOTE: Unused PLD inputs may be left floating. The programming software knows which input pins are unused, and engages an internal "pull-up" or "pull-down" device to keep the digital input at a known voltage level. Thus, it is not necessary for you to do this yourself.
     
  2. Demonstrate your "half gate" circuit to the instructor.
     
  3. Set up the 74HC4040 counter circuit to generate a four-bit input stimulus source. Use the Agilent 33120A function/arbitrary waveform generator to generate the squarewave clock signal needed by your counter circuit. Ensure that the squarewave switches between zero volts and five volts before you apply it to your circuit.
     
  4. Implement the Exponential Calculator in a GAL. Verify that your hardware meets specification for each of the sixteen possible inputs. Use the same MSO setup as last week.
     
  5. Demonstrate your finished circuit to the instructor.

All done!

bulletClean up your work area
bulletRemember to submit your lab notebook for grading at the beginning of next week's lab