module shiftregTB;

//Port modes
reg [3:0] A;   
reg [1:0] Sel;
reg clock;
wire [3:0] Q;
integer k;

//Instantiate DUT

shiftreg U1(
.A(A), .Sel(Sel), .clock(clock),
.Q(Q)
);

//Create an input stimulus

initial 

begin
	$monitor($time, "clock=%b A=%b Sel=%b Q=%b", 
		clock, A, Sel, Q);
	$shm_open("shiftregwaves.shm");
	$shm_probe("AC");

	//Initial values: Load the shift register
	clock = 0;
	A = 4'b0101;
	Sel = 11;
	#30
	Sel = 00;
	#30
	Sel = 11;
	#30
	Sel = 01;
	#30
	Sel = 11;
	#30
	Sel = 10;
	#30
	
	$finish;
end

always #5 clock = ~clock;
	

endmodule