module shiftreg(A,Sel,clock,Q);

//Port modes
input [3:0] A;   
input [1:0] Sel;
input clock;
output [3:0] Q;

//Registered identifiers
reg [3:0] Q;
reg [3:0] Y;

//Functionality

always @ (Sel or Q or A)
	case (Sel)
	0: Y <= {1'b0, Q[3:1]};
	1: Y <= {Q[2:0], 1'b0};
	2: Y <= Q;
	3: Y <= A;
	default: Q <= 4'b0000;
	endcase

always @ (posedge clock)
	Q <= Y;

endmodule