module alu(A,B,sum,Sel);

//Port modes
input [3:0] A,B;   
input [1:0] Sel;
output [3:0] sum;

//Registered identifiers
reg [3:0] sum;
reg [3:0] C;
reg Y;

//Functionality

always @ (Sel)
 Y <= Sel[0]^Sel[1];

always @ (B or Sel)
	case (Sel)
	0: C <= B;
	1: C <= ~B;
	2: C <= 4'b000;
	3: C <= 4'b1111;
	default: C <= 4'b0000;
	endcase

always @ (A or C or Y)
	begin
	sum<=A+C+Y;
	end

endmodule