module reg4bit(Din,Q, clock, reset);

//Port modes
input [3:0] Din;
input clock, reset;   
output [3:0] Q;

//Registered identifiers
reg [3:0] Q;

//Functionality

always @ (posedge clock or posedge reset)
	if (reset)
	Q<=0;
	else
	Q<=Din;

endmodule