module mux4to1(A,B,C,D,Sel,out);

//Port modes
input [3:0] A,B,C,D;   
input [1:0] Sel;
output [3:0] out;

//Registered identifiers
reg [3:0] out;

//Functionality

always @ (A or B or C or Sel)
	case (Sel)
	0: out <= A;
	1: out <= B;
	2: out <= C;
	3: out <= D;
	endcase

endmodule