module lock_TB;

//Port modes
reg clock, reset, A, B;
wire L;		

//Instantiate DUT

lock U1(
.clock(clock), .reset(reset), .A(A), .B(B), 
.L(L)
);

//Create an input stimulus

initial 

begin
	$shm_open("lockwaves.shm");
	$shm_probe("AC");

	//Initial values
	clock = 0;
	A=0;
	B=0;
	//reset the system
	reset = 1;
	#12
	reset = 0;
	#10
	//activate complete sequence to see if lock unlocks
	B=1;
	#10
	B=0;
	#20
	B=1;
	#10
	B=0;
	#20
	A=1;
	#10
	A=0;
	#20
	reset = 1;
	#10
	reset = 0;
	#40

	//activate sequence that should fail from xB state and see if it stays 
	//in the inactive state until reset is pressed
	B=1;
	#10
	B=0;
	#20
	A=1;
	#10
	A=0;
	#20
	B=1;
	#10
	B=0;
	#20
	reset = 1;
	#10
	reset = 0;
	#40

	//activate sequence that should fail from the xBB state
	B=1;
	#10
	B=0;
	#20
	B=1;
	#10
	B=0;
	#20
	B=1;
	#10
	B=0;
	#20
	reset = 1;
	#10
	reset = 0;
	#40

	//activate sequence that should fail from the xBBA state with B input
	B=1;
	#10
	B=0;
	#20
	B=1;
	#10
	B=0;
	#20
	A=1;
	#10
	A=0;
	#20
	B=1;
	#10
	B=0;
	#20
	reset = 1;
	#10
	reset = 0;
	#40

	//activate sequence that should fail from the xBBA state with B input
	B=1;
	#10
	B=0;
	#20
	B=1;
	#10
	B=0;
	#20
	A=1;
	#10
	A=0;
	#20
	A=1;
	#10
	A=0;
	#20
	reset = 1;
	#10
	reset = 0;
	#40

	$finish;

end

always #5 clock = ~clock;
	
endmodule