;**************************************************************
;;MC68HCS12 assembly code
;Program name:	hcs12atd.asm
;Origin:	page 417 of textbook by Cady & Sibigtroth
;modified: 	22 September 2005 by Jianjian Song
;Purpose:	Convert an analog signal on Channel 4 (PAD4 on Pin 9) and 
;		Scan mode is enabled to get a continuous reading. PAD4 is analog input
; by default once it is selected. Never use DDRAD to set PAD4 to be input.
; It would make PAD4 draw a huge amount of current.
;9-26-2005  --
; single channel and single conversion did not work. 
; Single channel and multiple conversion works fine.
;**************************************************************

; export symbols
        XDEF  ATD_INIT
        XDEF  ATD_CONVERT
        XREF	WAIT
        XREF  Xcor, Ycor, Zcor

ATD_Input1: equ mATDSTAT1_CCF4
ATD_Input2: equ mATDSTAT1_CCF5
ATD_Input3: equ mATDSTAT1_CCF6

; general constants
NLOOP:	EQU 	122	; 200 loops for 100 msec
RESOLUTION:	EQU	192	; 5000mv/256=19.5 mV
ATDMODE_CH1:	EQU	%10000100  ;
ATDMODE_CH2:  EQU %10000101
ATDMODE_CH3:  EQU %10000110



CodeSec: SECTION

ATD_INIT:
	BSET	ATDCTL2,mATDCTL2_ADPU	;  Power up the A/D
; wait for A/D converter to be ready for 100 microsec
	LDAA	#NLOOP	; 200 loops for
delay:	NOP          	; 800 clock cycles
	DBNE	A,delay
; Normal flag clearing, run in WAIT mode, no interrupts
	BCLR	ATDCTL2,mATDCTL2_AFFC|mATDCTL2_AWAI|mATDCTL2_ASCIE  ;at 0x82
	; one conversion per sequence
	BCLR	ATDCTL3,mATDCTL3_S4C  ;at 0x83
;	BSET	ATDCTL3,mATDCTL3_S1C  ;at 0x83
; Select 2 clock sample time and divide by 12 prescaler.
	BCLR	ATDCTL4,mATDCTL4_SMP0|mATDCTL4_SMP1	; Select 2 conversion clock periods
	BSET	ATDCTL4,mATDCTL4_PRS0	; divide by 12 conversion freq
	BSET	ATDCTL4,mATDCTL4_PRS2	; divide by 12 conversion freq
	BSET  ATDCTL4,mATDCTL4_SRES8  ; select 8 bit resolution ; at 0x84


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Started modifying from here   ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;display the voltage on channel 1
ATD_CONVERT:
CH1convert:

  PSHA
  PSHB

  LDAA  #ATDMODE_CH1
	STAA ATDCTL5		; Start the conversion by writing to ATDCTL5 at 0x85

spinCH1:	BRCLR	ATDSTAT1,ATD_Input1,spinCH1	; wait for conversion to complete at 0x8B
  BSET  ATDSTAT1, ATD_Input1 ; clear flag
	CLRA		; set A=0
	LDAB	ATDDR4L	; get 8-bt value from Channel 7 at 0x99F, which was how the module worked.
	LDAA  ATDDR4H 
	
	std Xcor
	
	PULB
	PULA
	
;display the voltage on channel 2  
CH2convert:  

  PSHA
  PSHB

  LDAA  #ATDMODE_CH2
	STAA ATDCTL5		; Start the conversion by writing to ATDCTL5 at 0x85

spinCH2:	BRCLR	ATDSTAT1,ATD_Input2,spinCH2	; wait for conversion to complete at 0x8B
  BSET  ATDSTAT1, ATD_Input2 ; clear flag
	CLRA		; set A=0
	LDAB	ATDDR4L	; get 8-bt value from Channel 7 at 0x99F, which was how the module worked.
  LDAA  ATDDR4H

  std Ycor

  PULB
  PULA

;display the voltage on channel 3
CH3convert:  

  PSHA
  PSHB

  LDAA  #ATDMODE_CH3
	STAA ATDCTL5		; Start the conversion by writing to ATDCTL5 at 0x85

spinCH3:	BRCLR	ATDSTAT1,ATD_Input3,spinCH3	; wait for conversion to complete at 0x8B
  BSET  ATDSTAT1, ATD_Input3 ; clear flag
	CLRA		; set A=0
	LDAB	ATDDR4L	; get 8-bt value from Channel 7 at 0x99F, which was how the module worked.
  LDAA  ATDDR4H
  
  std Zcor

  PULB
  PULA
  
  RTS	
  	

DONE:	BRA CH1convert
