//----- Testbench -----

// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
`timescale 1ns / 100ps

module TopLevel_TESTBENCH;

// Input stimulus:
reg	i$Clock;
reg	i$Invert;
reg	i$Enable;
reg	[3:0]	i$DataIn;

// Output connections:
wire	o$InvertLED;
wire	o$EnableLED;
wire	[6:0]	o$LeftSevenSeg;
wire	[6:0]	o$RightSevenSeg;
wire	o$MicroReset;
wire	o$RAMOE;


//Instantiate the DUT (device under test):
TopLevel DUT (
	// Inputs:
	.i$Clock ( i$Clock ),	// Master
	.i$Invert ( i$Invert ),	// Invert
	.i$Enable ( i$Enable ),	// Enable
	.i$DataIn ( i$DataIn ),	// Data

	// Outputs:
	.o$InvertLED ( o$InvertLED ),	// Displays
	.o$EnableLED ( o$EnableLED ),	// Displays
	.o$LeftSevenSeg ( o$LeftSevenSeg ),	// Left
	.o$RightSevenSeg ( o$RightSevenSeg ),	// Right
	.o$MicroReset ( o$MicroReset ),	// Hold
	.o$RAMOE ( o$RAMOE )	// Disable
);

	// Specify input stimulus:

initial begin

	// Initial values for input stimulus:
	i$Clock = 1'b0;
	i$Invert = 1'b0;
	i$Enable = 1'b0;
	i$DataIn = 4'h4;

	// Enable the core
	#30 i$Enable = 1'b1;

	// Enable inversion
	#30 i$Invert = 1'b1;

	// Change the input value
	#30 i$DataIn = 4'hd;

	// Disable inversion
	#30 i$Invert = 1'b0;

	// All done!
	#30 $finish;
end

	// Master clock
always #5 i$Clock = ~i$Clock;


endmodule