module XS40Demo (

	// Inputs:
	i$Clock,	// Master clock (12 MHz)
	i$Reset,	// Master reset (active high)

	// Outputs:
	o$Segments	// Periphery of 7-segment display
);

// Port mode declarations:
	// Inputs:
input	i$Clock;
input	i$Reset;

	// Outputs:
output	[5:0]	o$Segments;


// Registered identifiers:
// NOTE: Remove (or comment out) each line for which the 'assign' method is used
reg	[5:0]	o$Segments;
reg	r$Enable;
reg	[31:0] r$Counter;

// Functionality:

// Clock divider
always @ (posedge i$Clock or posedge i$Reset)
	if (i$Reset) begin
		r$Counter <= 0;
		r$Enable <= 0;
	end
	else begin
		if (r$Counter == 32'd2000000) begin
			r$Counter <= 0;
			r$Enable <= 1;
		end
		else
		begin
			r$Counter <= r$Counter + 1;
			r$Enable <= 0;
		end
	end

// Bit rotater
always @ (posedge i$Clock or posedge i$Reset)
	if (i$Reset)
		o$Segments <= 6'b100000;
	else if (r$Enable)
		o$Segments <= {o$Segments[0],o$Segments[5:1]};

endmodule