module Alive (
// Creates visual indicator of working FPGA
// (not an exhaustive test by any means, but can
// tell you that bitfile downloading process is working)

	// Outputs:
	o$LED

);

// Port mode declarations:
	// Outputs:
output	[6:0]	o$LED;

// Registered identifiers:
// NOTE: Remove (or comment out) each line for which the 'assign' method is used
reg	[6:0]	o$LED;

// Wire identifiers
wire w$Oscillator;
wire w$Clock;

// LED patterns
parameter p$Pattern1 =7'b0000001;
parameter p$Pattern2 =7'b0000010;
parameter p$Pattern3 =7'b0000100;
parameter p$Pattern4 =7'b0001000;
parameter p$Pattern5 =7'b0010000;
parameter p$Pattern6 =7'b0100000;
parameter p$Pattern7 =7'b1000000;

// Instantiate internal oscillator and global buffer
OSC4 oscut (.F8M(), .F500K(), .F16K(), .F490(), .F15(w$Oscillator) ); 
BUFG bufut (.I(w$Oscillator), .O(w$Clock)); 

// 7-bit shift register
always @ (posedge w$Clock)
	case (o$LED)
		p$Pattern1: o$LED <= p$Pattern2;
		p$Pattern2: o$LED <= p$Pattern3;
		p$Pattern3: o$LED <= p$Pattern4;
		p$Pattern4: o$LED <= p$Pattern5;
		p$Pattern5: o$LED <= p$Pattern6;
		p$Pattern6: o$LED <= p$Pattern7;
		p$Pattern7: o$LED <= p$Pattern1;
		default: o$LED <= p$Pattern1;
	endcase


endmodule